IBM paperweight teardown: Reverse-engineering 1970s memory chips

I recently received a vintage IBM paperweight from the early 1970s that showcases some memory chips.1 When IBM started using integrated circuits in the late 1960s, they packed the chips in square metal modules called Monolithic Systems Technology (MST). The paperweight illustrates the manufacturing steps for an MST module as a silicon wafer was cut into silicon dies, mounted on a square ceramic substrate, and wrapped in a thumbnail-sized metal package.

The paperweight contains a silicon wafer, four dies, and an MST module in various stages of assembly. The paperweight is somewhat yellowed with age. Click this image, or any other, for a larger photo.

Because the dies are encased in clear Lucite, it's possible to closely examine their circuitry and understand them better. The photo below is a closeup of the edge of the silicon wafer and the four dies inside the paperweight. The two larger dies are the same as the dies on the wafer. The two smaller dies are the same, but one is visibly damaged.2 For this blog post, I took detailed die photos using a microscope and reverse-engineered the smaller chip. My conclusion is that the larger chips are 1-kilobit static RAM chips, while the smaller ones are memory sense amplifiers.

Closeup of the dies and wafer inside the paperweight.

IBM System/370

These chips were probably used in IBM's popular System/370 line of mainframe computers. In 1964, IBM introduced the extremely successful System/360 family of mainframes. This product line was modernized in 1970 with the announcement of System/370, which was constructed from integrated circuits (unlike the System/360) and moved from magnetic core memory to semiconductor memory. The paperweight illustrates both of these changes: integrated circuits and semiconductor memory.

To understand the scale of a System/370 computer, the rendering below shows a System/370 Model 145. The Model 145 was a "medium-scale" machine in the middle of the System/370 family.3 The Model 145 is notable as IBM's first computer that used semiconductor main memory. The computer is very large by modern standards, filling the blue cabinets below. One cabinet holds the CPU while another holds 256 kilobytes of memory chips. This computer predates the microprocessor, so the CPU is built gate-by-gate from many boards of integrated circuits. The Model 145 weighed over a ton, cost $5 to 10 million (in current dollars), and was roughly as fast as an IBM PC (1981).

Rendering of a System/370 Model 145. The computer is the large blue cabinet along the wall. The white unit at the back is disk storage, while a card reader is in the foreground. Image by Oliver.obi, CC BY-SA 3.0.

The MST modules

In the earlier System/360, IBM didn't use integrated circuits, but instead used hybrid modules called SLT. For the System/370 IBM moved to integrated circuits, which they called "monolithics". While most companies packaged integrated circuits in rectangular plastic or ceramic packages, IBM retained the half-inch-square metal packages of SLT, calling it MST, for Monolithic Systems Technology.4 MST was a big improvement over the earlier hybrid SLT, about ten times more reliable and 4 to 8 times as dense. These MST integrated circuits were very simple by modern standards, with 32 transistors per module implementing about six gates, so thousands of integrated circuits were required to implement the computer.

The MST modules were manufactured in large quantities with automated production techniques. The sequence of components in the paperweight (below) illustrates the steps. On the left, the round silicon wafer is cut into individual dies. On the right, the square ceramic substrate has 16 holes for pins. Next, a printed-circuit pattern is applied to the substrate to connect the integrated circuit to the module's pins.5 In the third step, 16 pins are soldered to the substrate. Next, the silicon die and the ceramic substrate are combined, with the silicon die is mounted upside-down in the center of the ceramic substrate. Note how small the silicon die is, compared to the size of the package. The module is reflow-soldered, with contacts on the silicon die soldered directly to the substrate.6 Finally, the module is encased in metal, producing a half-inch square module. These modules give IBM's integrated circuits a unique appearance, distinct from the plastic or ceramic DIP integrated circuits used by other manufacturers.

The steps to manufacture an MST module.

The MST modules were tightly packed on circuit cards, such as the memory card below. The square module in combination with a four-plane printed circuit board provides considerably higher density than the circuit boards of other manufacturers at the time, which typically used DIP integrated circuits and 2-layer PCBs.

An IBM memory card packed with MST modules.

The memory wafer and chip

The silicon wafer in the paperweight is 2 inches in diameter, a size that was introduced in 1969. Wafer sizes have steadily increased since then and modern chip fabrication is done with much larger 300 mm (12") wafers.7 The wafer contains 177 dies; using a microscope, I created the die photo below of one of them. Curiously, the wafer is only partially manufactured; it looks like only one of the nine mask layers was constructed. Because this photo is taken from the wafer, you can see the test circuitry and alignment patterns in between the dies.

Die photo of one of the memory chips on the wafer. It is only partially manufactured. The part number "DLM1" is visible on it.

The paperweight also contains completed individual dies so I created the die photo below. The regular grid of memory cells is visible in the middle of the chip, with support circuitry around the edge. From studying the die and counting the cells, I think this is a 1-kilobit static RAM chip. Note the solder balls around the edge of the die, which allowed the chip to be soldered directly to the ceramic substrate. With 25 solder balls, this chip was probably mounted in an MST package with a 5×5 grid of pins.

Die photo of the memory chip.

Taking microscope photos is difficult when the die is encased in Lucite, so I wasn't able to see the circuitry under high magnification. As a result, I couldn't reverse-engineer this chip in detail.8 I was able to measure the feature size on the die as about 6µm, a process introduced around 1971.

The sense amplifier chip

The smaller die in the paperweight is much simpler with much larger components. I took the die photo below and found it contains 32 NPN transistors along with resistors. This chip is partially analog and also uses a type of logic called ECL. I believe the chip is a differential amplifier, a sense amplifier to read the signals from the memory chip. This would explain why the two chips are packaged together in the paperweight.

Die photo of the bipolar integrated circuit. The left and right sides are approximately mirror-images, with two copies of the same circuit.

In the die photo above, the silicon of the die is gray. Parts of the silicon were doped with arsenic, boron, or phosphorus to create regions with different semiconductor properties. The black lines in the silicon are boundaries between different doping levels. The yellowish regions are metal wiring on top of the silicon, connecting the various components together. The large black circles are the solder balls to connect the die to the MST substrate.

The diagram below is a detail from the chip, showing two types of resistors and a transistor. The upper resistor above is made from a line of higher-resistance N-type silicon, with metal contacts connected to either end. This forms a 65Ω resistor. The lower resistor has six contacts, providing multiple resistance values depending on where the metal lines are attached. It uses P-type silicon for the resistive element, providing hundreds of ohms of resistance. (There's a bit more internal structure to the resistors, but I'll ignore it.)

Two resistors and a transistor as they appear on the die.

The transistors are bipolar NPN transistors, but their structure is a bit more complex than the typical NPN transistor. Physically, they have two bases and two collectors wired together to reduce current density, so you'll see five metal connections to each transistor. The diagram below shows the cross-section structure of the transistor. The five metal connections on top of the cross-section correspond to the five connections on the transistor above. The collector, base, and emitter are connected to N-P-N layers, forming the NPN transistor.9 The P+ ring provides isolation around the transistor.

This diagram shows the internal structure of the chip's transistors, based on patent 3539876.

By recognizing the components on the die and tracing out the wiring, the circuit can be reverse-engineered. However, if you look at the die closely, you'll see that many components are not connected. The reason is that IBM used a technique called "master slice" to produce a variety of integrated circuits without custom-designing each one.10 The idea was to use a common silicon die with multiple transistors and resistors. By modifying the metal layer (which was relatively inexpensive), the components could be wired into the desired circuits. This is also why the resistors had multiple taps, so they could be wired to obtain different values as needed.

The differential amplifier and ECL logic

Logic circuits can be built in a wide variety of ways. Almost all computers today use a logic family called CMOS (complementary metal-oxide-semiconductor), building gates out of MOS transistors. However, the IBM System/370 used a high-performance11 logic family known as Emitter-coupled logic (ECL), which IBM called Current-Switch Emitter Follower (CSEF).12 ECL was invented at IBM in 1956 for use in IBM's high-performance transistorized computers.

ECL is based on a differential pair, a circuit that amplifies the difference between two inputs. (This circuit is also the basis of op-amps.) The idea behind a differential pair (below) is that a fixed current flows through the circuit. If the left input is a higher voltage than the right, the left transistor will turn on and most current will flow through the left branch (red). Conversely, if the right input is a higher voltage than the left, the right transistor will turn on and most current will flow through the right branch (blue). The differential pair provides amplification because a small difference in the inputs will create a large shift in the current.

A differential pair amplifies the difference between the two inputs.

The above circuit is used as an amplifier in the chip, but with a few modifications it also forms an ECL gate. For a gate, the voltage into one branch is fixed at a reference voltage, midway between the "0" level and the "1" level. Thus, if the input is higher than the reference voltage, it will be considered a "1", and lower will be a "0". (MST chips used ground as the reference voltage.4) The ECL circuit below is an inverter, since if the input is high, the current through the left resistor will pull the output low. To improve performance, the bottom resistor has been replaced with a current sink circuit (purple). The current through the current sink is set by an external bias voltage (V_CS).

The differential pair can be modified to produce an ECL inverter.

A buffer (green) has been added to the output above. The buffer circuit is called an emitter follower since the output is taken from the transistor's emitter and the output follows the input. This is why IBM used the name Current-Switch Emitter Follower for this logic family.

The sense amplifier chip's circuitry

I reverse-engineered the chip's circuitry and found it contains two copies of the circuit below. This circuit is a differential amplifier, probably used as a sense amplifier to amplify the outputs from the memory chip and convert them to logic signals.13

The chip takes two inputs, a negative input and a positive input, and produces a logic-level output. The circuit is a bit complicated, but I'll try to explain the highlights. The differential amplifiers (discussed earlier) are the core of the chip. The input signals are buffered and then go into the lower amplifier (green box). The outputs from that amplifier go into the upper amplifier. Cascading two amplifier stages in this way makes the chip very sensitive, providing a large degree of amplification.

Reverse-engineered schematic of the sense amplifier chip.

The yellow boxes are buffers, using the emitter-follower circuit described earlier. One buffer is used on each input and one on the output. The purple box is an ECL gate. I believe it is used to latch the amplifier's value by feeding the output back in. The current sink transistors are colored blue to distinguish them. They provide a constant current to the differential amplifiers and other circuits.

Conclusion

Well, this is a lot of analysis for a paperweight. But this paperweight provides an interesting window into IBM's technology of 1974.14 In particular, it illustrates IBM's transition to integrated circuits and semiconductor memory for the System/370 mainframes. It also explains IBM's unique construction technique for integrated circuits, packaging them on a ceramic wafer in a square metal can, a technology they called MST. Finally, the paperweight's 1-kilobit memory chip shows the amazing progress that memory technology has made over the past decades, giving us megabit chips and now multi-gigabit chips.

Thanks to @magnetic_tape for sending me the paperweight. Thanks to Mark Smotherman for information on MST. I announce my latest blog posts on Twitter, so follow me @kenshirriff. I also have an RSS feed. If you're interested in old IBM technology, see my recent post on an IBM Technology Box, covering 1948 to 1986.

Notes and references

1. The text "Essones" on the paperweight refers to IBM's semiconductor plant in Corbeil-Essones, a suburb of Paris. IBM opened this plant in 1964, Europe's biggest semiconductor factory at the time. ↩

2. Curiously, one of the dies in the paperweight is damaged and has a corner missing. Note that it's not simply broken, since the metal layer and the silicon doping don't go to the edge. Probably this die is from the edge of the wafer so it didn't get fully exposed. With the incomplete wafer and the truncated die, it's clear that they were using junk parts in the paperweights.

   

   One die in the paperweight is damaged.

    ↩

3. For a while, IBM used a rational numbering system for the System/370 models, with computer power increasing with the model number. Model numbers ranged from the low-end Model 115 to the high-end Model 195. However, the numbering system fell apart in the late 1970s as systems were assigned seemingly-random numbers such as 3031, 4361, 3090, and 9370. Despite having the biggest number, the 9370 was a low-end machine. See IBM's 360 and Early 370 Systems for a detailed history of the System/370. ↩

4. IBM had multiple versions of MST logic for different products; some versions used different voltages. MST-1 uses ground as the upper voltage, -4 volts as the lower voltage, and -1.32 volts as the ECL reference voltage. (Because ECL circuits are more sensitive to fluctuations in the upper voltage, ECL families often assign that level to ground, making the lower voltage negative.) MST-2 shifts the levels so the reference level is ground; the upper voltage is +1.25V and the lower is -3V.

   I couldn't find much information on the other MST variants, but for reference I'll summarize what I did find. MST-2 was used in the S/370 Models 145 and 155, while MST-4 was a high-performance version developed by Texas Instruments and used in the S/360 Model 85. The S/370 Model 168 used MST-1, MST-2, MST-4, and MST-A. The System/3 used MST-10. The IBM 3889 OCR machine, 3350 Disk Storage, and 3704 Communications Controller used MST-1 and MST-E. The IBM 3031 used MST-1, MST-2, MST-4, MST-4E, MST-E, and MST-A. Other versions included MST-195 and MST-255. ↩↩

5. The MST ceramic substrate provides the interface between two circuitry scales: the printed circuit board scale with 0.125-inch pin spacing, and the integrated circuit scale with 0.01-inch solder ball spacing. The pattern on the MST ceramic substrate has some interesting subtleties; each power pin is connected to three solder balls, allowing more current into the IC. The trace for V- crosses the chip, providing two connections on one side and on on the other. The trace for V+ extends into the middle of the IC to provide additional power connections.

   

   Diagram showing how the chip is mounted on the ceramic substrate. (The chip image has been mirrored to account for it being mounted upside down.)

   For some reason, MST uses two different pin-numbering schemes. The 12-pin SLT numbering was extended by spiraling 13-16 into the middle. But the more common MST pin names are A01 through D04.

    ↩

6. IBM called the chip mounting technique "controlled-collapse chip connections" or C-4. It used a controlled volume of solder to make electrical and mechanical contact with the module. During soldering, the chip was pulled into alignment with the module fingers by surface tension, similar to how a surface-mount device is soldered today. For more details, see Design of Logic Circuit Technology for IBM System/370 Models 145 and 155. ↩

7. Information on wafer sizes is here and on Wikipedia. ↩

8. The photo below is the best resolution I could get of the memory cells. I believe this is six memory cells; I put a box around one. The circuitry in two rows is connected as shown in blue. This is probably two cross-coupled inverters, a standard circuit for a static RAM cell.

   

   Closeup of six memory cells in the memory chip.

    ↩

9. The diagram below provides more details on the construction and dimensions of the transistors.

   

   The transistors in the MST chips have a single base and collector but has two base and collector connections to reduce current density. Image from Design of Logic Circuit Technology for IBM System/370 Models 145 and 155.

    ↩

10. The master slice approach used a fixed silicon layout with transistors and resistors, but changed the metal interconnections to create different chips, a process called "personalization". The diagram below, from patent 3539876, shows a silicon layout used for IBM's master slice integrated circuits. If you match up the resistors and transistors, this diagram is almost identical to the die in the paperweight. There are a few differences, though. In particular, the die has an extra pin on the left and right, with slight resistor changes to accommodate them. Design of Monolithic Circuit Chips (1966) describes the origins of the master slice approach. Even in 1966, they were using computer-assisted design for integrated circuits.

    

    The die structure from patent 3539876 is almost identical to the chip.

     ↩

11. ECL gates obtained much of their speed advantage because the transistors were not completely turned on (i.e. saturated). This allowed the transistors to switch the current path rapidly. Additionally, the difference between a "0" voltage and a "1" voltage was small (about 0.8) volts, so signals could switch between the two voltages quickly. In comparison, TTL gates typically had a difference of about 3.2 volts between a "0" and a "1", requiring more time to switch. (Signals could typically switch at about 1 volt per nanosecond, so a larger voltage swing caused nanoseconds of delay.) On the other hand, the small voltage swings of ECL made the circuits more sensitive to electrical noise. ↩

12. For more details on ECL logic and how IBM used it, see Design of Logic Circuit Technology for IBM System/370 Models 145 and 155. ↩

13. I'm not completely sure of the role of this chip. I searched extensively, but couldn't find any documentation on it. IBM's MST modules are described in detail in MST-2 Module Data (1974). Inconveniently, the chip's part number (2551667) doesn't appear in this document (although nearby part numbers such as 2551665 are described). Thus, I had to study the circuit to determine its function. At first I expected it to be a standard logic gate. However, the two amplification stages didn't make sense, or the complementary inputs. Another possibility was that it converted differential signals (such as from the Differential Current Switch logic family) into ECL signals. That would explain the differential inputs, but not the two stages of amplification.

    I think it's most likely that the chip is acting as a sense amplifier for memory chip, amplifying the memory chip's output and turning it into a logic level. The 370 Model 45 hardware manual (page 3-9) describes a sense latch module used with its memory, so external sense amplifiers were used in System/370. The chip pin that I've labeled "latch" may be used to feed back the output to latch it, or it may be used as an enable pin or to reset the latch; without seeing the surrounding circuitry, I'm not sure.

    Intel also produced memory chips that required external sense amplifiers; see the Intel 1103 and Intel 2105. Intel produced sense amplifier chips, the 3208 and 3408 Hex Sense Amplifiers specifically to provide external sense amplifies for memory. One motivation for external sense amplifiers was that memory chips were built with MOSFET transistors, but bipolar transistors produced better amplifiers. Later memory chips, though, included the sense amplifiers on the chip. ↩

14. I'm guessing that the module is from 1974. Based on the technology, the paperweight is from the early 1970s. The module is labeled with the code "1 425C404". My theory is that the second digit "4" indicates the year, dating the module to 1974. IBM's modules are usually labeled with three lines of text, but there's no solid information on the meanings. The first line is the part number. The second line is believed to indicate the manufacturing location. (So "IBM 52" would indicate Essones, France. Although a reader tells me that IBM 52 was Poughkeepsie or Fishkill NY, while IBM 29 was Essex.) The third line is believed to be a date/lot code. Studying an extensive collection of cards, the digit after the 1 appears to be the year. For instance, some codes start with "1712" for 1977, "1 949" and "1925" for 1979, "1-005" and "1 031" for 1980, "1-106" for 1981, "1 205" for 1982, "1 444" for 1984, "1 865" for 1988, "1912" for 1989. But other modules have codes starting with "1 E52", "1 F09", and "1 H27" so it's not quite that simple. There also are a few codes like "1 8450" for 1984, suggesting they also used 2-digit year codes. It's possible that different sites used different codes. ↩

The core memory inside a Saturn V rocket's computer

The Launch Vehicle Digital Computer (LVDC) had a key role in the Apollo Moon mission, guiding and controlling the Saturn V rocket. Like most computers of the era, it used core memory, storing data in tiny magnetic cores. In this article, I take a close look at an LVDC core memory module from Steve Jurvetson's collection. This memory module was technologically advanced for the mid-1960s, using surface-mount components, hybrid modules, and flexible connectors that made it an order of magnitude smaller and lighter than mainframe core memories.2 Even so, this memory stored just 4096 words of 26 bits.1

A core memory module from the LVDC. This module stored 4K words of 26 data bits and 2 parity bits. It weighs 2.3 kg (5.1 pounds) and measures about 14 cm×14 cm×16 cm (5½"×5½"×6"). Click on any photo for a larger version.

The race to the Moon started on May 25, 1961 when President Kennedy stated that America would land a man on the Moon before the end of the decade. This mission required the three-stage Saturn V rocket, the most powerful rocket ever built. The Saturn V was guided and controlled by the Launch Vehicle Digital Computer3 (below), from liftoff into Earth orbit, and then on a trajectory towards the Moon. (The Apollo spacecraft separated from the Saturn V rocket at that point, ending the LVDC's role.)

The LVDC mounted in a support frame. The round connectors are visible on the front side of the computer. There are 8 electrical connectors and two connectors for liquid cooling. Photo courtesy of IBM.

The LVDC was just one of several computers onboard the Apollo mission. The LVDC was connected to the Flight Control Computer, a 100-pound analog computer. The Apollo Guidance Computer (AGC) guided the spacecraft to the Moon's surface. The Command Module contained one AGC while the Lunar Module contained a second AGC7 along with the Abort Guidance System, an emergency backup computer.

Multiple computers were onboard an Apollo mission. The Launch Vehicle Digital Computer (LVDC) is the one discussed in this blog post.

Unit Logic Devices (ULD)

The LVDC was built with an interesting hybrid technology called ULD (Unit Logic Devices). Although they superficially resembled integrated circuits, ULD modules contained multiple components. They used simple silicon dies, each implementing just one transistor or two diodes. These dies, along with thick-film printed resistors, were mounted on a half-inch-square ceramic wafer to implement a circuit such as a logic gate. These modules were a variant of the SLT (Solid Logic Technology) modules developed for IBM's popular S/360 series of computers. IBM started developing SLT modules in 1961, before integrated circuits were commercially viable, and by 1966 IBM produced over 100 million SLT modules a year.

ULD modules were considerably smaller than SLT modules, as shown in the photo below, making them more suitable for a compact space computer.4 ULD modules used ceramic packages instead of SLT's metal cans, and had metal contacts on the upper surface instead of pins. Clips on the circuit board held the ULD module in place and connected with these contacts.5 The LVDC and associated hardware used more than 50 different types of ULDs.

SLT modules (left) are considerably larger than ULD modules (right). A ULD module is 7.6 mm × 8 mm.

The photo below shows the internal components of a ULD module. On the left, the circuit traces are visible on the ceramic wafer, connected to four tiny square silicon dies. While this looks like a printed circuit board, keep in mind that it is much smaller than a fingernail. On the right, the black rectangles are thick-film resistors printed onto the underside of the wafer.

Top and underside of a ULD showing the silicon dies and resistors. While SLT modules had resistors on the upper surface, ULD modules had resistors underneath, increasing the density but also the cost. From IBM Study Report Figure III-11.

The microscope photo below shows a silicon die from a ULD module that implements two diodes.6 The die is very small; for comparison, grains of sugar are displayed next to the die. The die had three external connections through copper balls soldered to the three circles. The two lower circles were doped (darker regions) to form the anodes of the two diodes, while the upper-right circle was the cathode, connected to the substrate. Note that this die is much less complex than even a basic integrated circuit.

Photo of a two-diode silicon die next to sugar crystals. This photo is a composite of top-lighting to show the die details, with back-lighting to show the sugar.

How core memory works

Core memory was the dominant form of computer storage from the 1950s until it was replaced by semiconductor memory chips in the 1970s. Core memory was built from tiny ferrite rings called cores, storing one bit in each core by magnetizing the core either clockwise or counterclockwise. A core was magnetized by sending a pulse of current through wires threaded through the core. The magnetization could be reversed by sending a pulse in the opposite direction.

To read the value of a core, a current pulse flipped the core to the 0 state. If the core was in the 1 state previously, the changing magnetic field created a voltage in a sense wire threaded through the cores. But if the core was already in the 0 state, the magnetic field wouldn't change and the sense wire wouldn't pick up a voltage. Thus, the value of the bit in the core was read by resetting the core to 0 and testing the sense wire. An important characteristic of core memory was that the process of reading a core destroyed its value, so it needed to be re-written.

Using a separate wire to flip each core would be impractical, but in the 1950s a technique called "coincident-current" was developed that used a grid of wires to select a core. This depended on a special property of cores called hysteresis: a small current has no effect on a core, but a current above a threshold would magnetize the core. This allowed a grid of X and Y lines to select one core from the grid. By energizing one X line and one Y line each with half the necessary current, only the core where both lines crossed would get enough current to flip leaving the other cores unaffected.

Closeup of an IBM 360 Model 50 core plane. The LVDC and Model 50 used the same type of cores, known as 19-32 because their inner diameter was 19 mils and their outer diameter was 32 mils (0.8 mm). While this photo shows three wires through each core, the LVDC used four wires.

The photo below shows one core plane from the LVDC's memory.8 This plane has 128 X wires running vertically and 64 Y wires running horizontally, with a core at each intersection. For reading, a single sense wire runs through all the cores parallel to the Y wires. For writing, a single inhibit wire (explained below) runs through all the cores parallel to the X wires. The sense wires cross over in the middle of the plane; this reduces induced noise because noise from one half of the plane cancels out noise from the other half.

One core plane for the LVDC's memory, holding 8192 bits. Connections to the core plane are made through the pins around the outside. From Smithsonian National Air and Space Museum.

The plane above had 8192 locations, each storing a single bit. To store a word of memory, multiple core planes were stacked together, one plane for each bit in the word. The X and Y select lines were wired to zig-zag through all the core planes, in order to select a bit of the word from each plane. Each plane had a separate sense line for reading, and a separate inhibit line for writing. The LVDC memory used a stack of 14 core planes (below), storing a 13-bit "syllable" along with a parity bit.10

The LVDC core stack consists of 14 core planes. This stack is at the US Space & Rocket Center. Photo from NCAR EOL. I retouched the photo to reduce distortion from the plastic case.

Writing to core memory required additional wires called the inhibit lines. Each plane had one inhibit line threaded through all the cores in the plane. In the write process, a current passed through the X and Y lines, flipping the selected cores (one per plane) to the 1 state, storing all 1's in the word. To write a 0 in a bit position, the plane's inhibit line was energized with half current, opposite to the X line. The currents canceled out, so the core in that plane would not flip to 1 but would remain 0. Thus, the inhibit line inhibited the core from flipping to 1. By activating the appropriate inhibit lines, any desired word could be written to the memory.

To summarize, a core memory plane had four wires through each core: X and Y drive lines, a sense line, and an inhibit line. These planes were stacked to form an array, one plane for each bit in the word. By energizing an X line and a Y line, one core in each plane was selected. The sense line was used to read the contents of the bit, while the inhibit line was used to write a 0 (by inhibiting the writing of a 1).9

The LVDC core memory module

In this section, I'll explain how the LVDC core memory module was physically constructed. At its center, the core memory module contains the stack of 14 core planes shown earlier. This is surrounded by multiple boards with the circuitry to drive the X and Y select lines and the inhibit lines, read the bits from the sense lines, detect errors, and generate necessary clock signals.11

An exploded view of the memory module showing the key components. An MIB (Multilayer Interconnection Board) is a 12-layer printed circuit board. From Saturn V Guidance Computer Progress Report Fig 2-43.

Memory Y driver panel

A word in core memory is selected by driving the appropriate X and Y lines through the core stack. I'll start by describing the Y driver circuitry and how it generates a signal through one of the 64 Y lines. Instead of having 64 separate driver circuits, the module reduces the amount of circuitry by using 8 "high" drivers and 8 "low" drivers. These are wired up in a "matrix" configuration so each combination of a high driver and a low driver selects a different line. Thus, the 8 high drivers and 8 low drivers select one of the 64 (8×8) Y lines. The footnote12 has more information on the matrix technique.

The Y driver board (front) drives the Y select lines in the core stack.

The closeup view below shows some of the ULD modules (white) and transistor pairs (golden) that drive the Y select lines. The "EI" module is the heart of the driver; it supplies a constant voltage pulse (E) or sinks a constant current pulse (I) through a select line.14 A select line is driven by activating an EI module in voltage mode at one end of the line and an EI module in current mode at the other end. The result is a pulse with the correct voltage and current to flip the core. It takes a hefty pulse to flip a core; the voltage pulse is fixed at 17 volts, while the current is adjusted from 180 mA to 260 mA depending on the temperature.13

Closeup of the Y driver board showing six ULD modules and six transistor pairs. Each ULD module is labeled with an IBM part number, the module type (e.g. "EI"), and an unknown code.

The board also has error-detector (ED) modules that detect if more than one Y select line is driven at the same time. Implementing this with digital logic would require a complicated set of gates to detect if two or more of the 8 inputs are high. Instead, the ED module uses a simple semi-analog design: it sums the input voltages using a resistor network. If the resulting voltage is above a threshold, the output is triggered.

A diode matrix is underneath the driver board, containing 256 diodes and 64 resistors. This matrix converts the 8 high and 8 low pairs of signals from the driver board into connections to the 64 Y lines that pass through the core stack. Flex cables on the top and bottom of the board connect the board to the diode matrix. Two flex cables on the left (not visible in the photo) and two flex cables on the right (one visible) connect the diode matrix to the core stack.15 The flex cable visible on the left connects the Y board to the rest of the computer via the I/O board (described later) while a small flex cable on the lower right connects to the clock board.

Memory X driver panel

The circuitry to drive the X lines is similar to the Y circuitry, except there are 128 X lines compared to 64 Y lines. Because there are twice as many X lines, the module has a second X driver board underneath the one visible below. Although the X and Y boards have the same components, the wiring is different.

This board and the similar one underneath drive the X select lines in the core stack.

The closeup below shows that the board has suffered some component damage. One of the transistors has been dislodged, a ULD module has been broken in half, and the other ULD module is cracked. The wiring is visible inside the broken module as well as one of the tiny silicon dies (on the right). This photo also shows vertical and horizontal circuit board traces on several of the board's 12 layers.

A closeup of the X driver board showing some damaged circuitry.

Underneath the X driver boards is the X diode matrix, containing 288 diodes and 128 resistors. The X diode matrix uses a different topology than the Y diode board to avoid doubling the number of components.16 Like the Y diode board, this board contains components mounted vertically between two printed circuit boards. This technique is called "cordwood" and allows the components to be packed together closely.

Closeup of X diode matrix showing diodes mounted vertically using cordwood construction between two printed circuit boards. The two X driver boards are above the diode board, separated from it by foam. Note how the circuit boards are packed very closely together.

Memory sense amplifiers

The photo below shows the sense amplifier board on top of the module.17 It has 7 channels to read 7 bits from the memory stack; an identical board below processes another 7 bits, for 14 bits in total. The job of the sense amplifier is to detect the small signal (20 millivolts) generated by a flipping core, and turn it into a 1-bit output. Each channel consists of a differential amplifier and buffer, followed by a differential transformer and an output latch. At the left, the 28-conductor flex cable connects to the memory stack, feeding the two ends of each sense wire into the amplifier circuitry, starting with an MSA-1 (Memory Sense Amplifier) module. The discrete components are resistors (brown cylinders), capacitors (red), transformers (black), and transistors (golden). The data bits exit the sense amplifier boards through the flex cable on the right.

The sense amplifier board on top of the memory module. This board amplifies the signals from the sense wires to produce the output bits.

Memory inhibit drivers

The inhibit board is on the underside of the core module and holds the inhibit drivers that are used for writing to memory. There are 14 inhibit lines, one for each plane in the core stack. To write a 0 bit, the corresponding inhibit driver is activated and the current through the inhibit line prevents the core from flipping to a 1. Each line is driven by an ID-1 and ID-2 (Inhibit Driver) module and a pair of transistors. The high-precision 20.8Ω resistors at the top and bottom of the board regulate the inhibit current. The 14-wire flex cable on the right connects the drivers to the 14 inhibit wires in the core stack.

The inhibit board on the bottom of the memory module. This board generates the 14 inhibit signals used during writing.

Memory clock driver

The clock driver is a pair of boards that generate the timing signals for the memory module. Once the computer starts a memory operation, the various timing signals used by the memory module are generated asynchronously by the module's clock driver. The clock driver boards are on the bottom of the module, between the core stack and the inhibit board so it is hard to see the boards.

The clock driver boards are below the core memory stack but above the inhibit board.

The photo above looks between the clock driver boards; the inhibit board is on the bottom. The blue components are multi-turn potentiometers, presumably to adjust timings or voltages. Resistors and capacitors are also visible on the boards. The schematic shows several MCD (Memory Clock Driver) modules, but I can't see any modules on the boards. I don't know if that is due to the limited visibility, a change in the circuitry, or another board with these modules.

Memory input-output panel

The final board of the memory module is the input-output panel (below), which distributes signals between the boards of the memory module and the remainder of the LVDC computer. At the bottom, the green 98-pin connector plugs into the LVDC's memory chassis, providing signals and power from the computer. (Much of the connector's plastic is broken, exposing the pins.) The distribution board is linked to this connector by two 49-pin flex cables at the bottom (only the front cable is visible). Other flex cables distribute signals to the X-driver board (left), the Y-driver board (right), the sense amplifier board (top), and inhibit board (underneath). The 20 capacitors on the board filter the power supplied to the memory module.

The input-output board is the interface between the memory module and the rest of the computer. The green connector at the bottom plugs into the computer, and these signals are routed through flat cables to other parts of the memory module. This board also has filter capacitors.

Conclusion

The LVDC's core memory module provided compact, reliable storage for the computer. The lower half of the computer (below) was filled by up to 8 core memory modules. This allowed the computer to hold a total of 32 kilowords of 26-bit words, or 16 kilowords in redundant high-reliability "duplex" mode.18

The LVDC held up to eight core memory modules. Photo at US Space & Rocket Center, courtesy of Mark Wells.

The core memory module provides an interesting view of a time when 8K of storage required a 5-pound module. While this core memory was technologically advanced for its time, the hybrid ULD modules were rapidly obsoleted by integrated circuits. Core memory as a whole died out in the 1970s with the advent of semiconductor DRAMs.

The contents of core memory are retained when the power is disconnected, so it's likely that the module still holds the software from when the computer was last used, even decades later. It would be interesting to try to recover this data, but the damaged circuitry poses a problem so the contents will probably remain locked inside the memory module for decades more.

I announce my latest blog posts on Twitter, so follow me @kenshirriff for future articles. I also have an RSS feed. For an explanation of core memory, see CuriousMarc's video where we wire up a core plane and demonstrate how it works. I've written before about core memory in the IBM 1401, core memory in the Apollo Guidance Computer, and core memory in the IBM S/360. Thanks to Steve Jurvetson for supplying the core array.

Notes and references

1. A word size of 26 bits may seem bizarre, but in the 1960s computers hadn't yet standardized on bytes and word sizes that were a power of two. Business computers often used 6-bit characters, while aerospace computers typically used whatever word size provided the necessary accuracy. ↩

2. It's interesting to compare the size of the LVDC's core memory to IBM's commercial core memories, which I wrote about here. The 128-kilobyte expansion for the IBM S/360 Model 40 computer required an additional cabinet weighing 610 pounds and measuring 62.5"×26"×60". An LVDC core memory module holds 4K words of 26 bits, equivalent to 13 kilobytes. Doing the math, the LVDC has 1/12 the weight and 1/40 the volume per byte. The core stack itself was very similar between the LVDC and the S/360 machines; the difference in weight and volume comes from the surrounding electronics and packaging. ↩

3. For more information on the LVDC, see the Virtual AGC project's LVDC page. Also see the interesting SmarterEveryDay video on the LVDC. Fran Blanche did an extensive investigation into an LVDC circuit board. ↩

4. The SLT modules in my photograph are mounted on an SMS card, rather than the expected SLT card. SMS cards were IBM's previous generation of circuit cards and normally used discrete germanium transistors. However, even after the introduction of SLT in 1964, IBM needed to support older computers with SMS cards. To reduce costs, they started building old-style SMS cards that used the more modern SLT modules. The point is that SLT modules were usually packed densely on multiple-layer circuit boards, rather than the low-density SMS card in the photo. ↩

5. One question is why did IBM use SLT modules instead of integrated circuits? The main reason was that integrated circuits were still in their infancy, having been invented in 1959. In 1963, SLT modules had cost and performance advantages over integrated circuits. However, SLT modules were viewed outside IBM as backward compared to integrated circuits. One advantage of SLT modules over integrated circuits was that the resistors in SLT were much more accurate than those in integrated circuits. During manufacturing, the thick-film resistors in SLT modules were carefully sand-blasted to remove resistive film until they had the desired resistance. SLT modules were also cheaper than comparable integrated circuits in the 1960s. By 1969, IBM started using integrated circuits, which they called MST (Monolithic Systems Technology). IBM packaged their integrated circuits in SLT-style metal packages, rather than the industry-standard DIP epoxy packages. Chapter 2 of IBM's 360 and Early 370 Systems discusses the history of SLT modules in great detail. ↩

6. Curiously, the ULD modules in the core memory did not contain any sealant inside. In contrast, the ULD modules examined by Fran Blanche were filled with pink silicone inside. ↩

7. It's interesting to compare the AGC to the LVDC since they took two very different approaches to computer design and manufacture. Both computers had rectangular metal boxes, magnesium-lithium for the LVDC and magnesium for the AGC. Physically, the LVDC was about twice the size (2.2 cubic feet vs 1.1 cubic feet) even though they were both about 70 pounds. The LVDC used 138 Watts and was liquid-cooled, while the AGC used 55 watts and was cooled by conduction. The LVDC used 26-bit words compared to 15 bits in the AGC. One big architectural difference was that the LVDC was a serial computer, operating on one bit at a time, while the AGC operated on all bits in parallel (like most computers). Another important difference was that the LVDC used triple redundancy for reliability, while the AGC had no hardware fault handling. Both computers used a 2.048 MHz clock, but the LVDC was considerably slower because it was serial: 82 µs for an add operation compared to 23.4 µs for the AGC. The LVDC had up to 8 core memory modules, holding 4K words each. The AGC's core memory was only 2K words. However, the AGC also had 36K words of read-only storage in its hardwired core rope modules. (The LVDC did not use core rope.)

   The two computers were constructed in very different ways. The AGC was built from integrated circuits, while the LVDC used hybrid ULD modules. The AGC's logic gates were RTL (resistor-transistor logic) NOR gates, while the LVDC's were slightly more advanced DTL (diode-transistor logic) AND-OR-INVERT gates. While the AGC used two types of ICs (a dual NOR gate and a sense amplifier), the LVDC used many different types of modules.

   The AGC's circuit boards were encapsulated into rectangular modules, while the LVDC's circuit boards plugged into a backplane in a more standard way. The AGC's backplane was wire-wrapped by machine, while the LVDC's backplane was a 14-layer printed circuit board.

   IBM engaged in political battles, attempting to replace MIT's AGC with the LVDC. IBM argued that the AGC wasn't reliable enough compared to the triple-redundant LVDC. According to MIT, however, the AGC could run a guidance program 10 to 20 times faster than the LVDC, use half the memory, and provide more accuracy (by using double precision). MIT argued that the LVDC wasn't powerful enough to replace the AGC. In the end, the AGC survived the "naysayers" and was used on the Apollo spacecraft, while the LVDC had its role in the Saturn V rocket. The "showdown" is described in more detail here.  ↩

8. The Smithsonian website states that the core plane is approximately 4"×7"×1", but that can't be right since the entire memory module is less than 7" wide. The Study Report page 3-43 says each plane is 5.5"×3.5×0.15", which seems accurate. ↩

9. The book Memories That Shaped an Industry discusses the history of core memory at IBM. ↩

10. The LVDC has 26-bit words, each word consisting of two 13-bit syllables. Its core memory is described as holding 4K words, where each word is 26 data bits and 2 parity bits. However, the core memory is physically constructed to store 8K syllables (13 data bits and 1 parity bit). Thus, two memory accesses are required to read a complete word. An instruction is one 13-bit syllable so an instruction can be read in a single memory cycle. Thus, executing a typical instruction requires three memory accesses: one for the instruction and two for the data. (Keep in mind that reading from core memory erases the data, so a memory access consists of a read followed by a write to restore the data.) ↩

11. Much of the memory-related circuitry is in the LVDC's computer logic, not the memory module itself. In particular, the computer's logic contains registers to hold the address and data word and convert between serial and parallel. It also contains circuitry to decode the address into drive lines, as well as to generate and check parity. ↩

12. Core memories typically used a "matrix" approach to reduce the number of circuits required to drive the X and Y select lines. The diagram below demonstrates this technique for the vertical lines in a hypothetical 9×5 core array. There are three "high" drivers (A, B and C), and three "low" drivers (1, 2 and 3). If driver B is energized positive and driver 1 is energized negative, current flows through the core line highlighted in red. By selecting a different pair of drivers, a different line is energized. In a large array, this approach significantly reduces the number of line drivers required.

    

    The "matrix" approach reduces the number of line drivers required.

    When using a matrix approach, each line must have diodes to prevent "sneak paths" through the cores. To see the need for diodes, note that in the example above current could flow from B to 2, up to A and finally down to 1, for instance, incorrectly energizing multiple lines and flipping the wrong cores. By putting diodes on each line, reverse current paths such as 2 to A can be blocked. Also note that writing core memory requires current pulses in the opposite direction from reading. Supporting this requires additional diodes in the opposite direction. ↩

13. Because the characteristics of ferrite cores change with temperature, the memory module adjusts the current based on temperature, from 260 mA at 10 °C to 180 mA at 70 °C. A sensor in the stack detects the temperature, causing a TCV regulator (Temperature Controlled Voltage) to generate a voltage ranging from 6 V at 10 °C to 4 V at 70 °C. The TCV control voltage is fed into each EI module, causing the current to drop 1.33 mA per °C.  ↩

14. It's unclear why the driver boards use EI modules as well as ID-2 (Inhibit Driver) modules, since a separate board implements the inhibit drivers. The earlier schematics show just the EI modules. (See Laboratory Maintenance Instructions for LVDC Vol. II (1965) page 10-164 for the schematics.) The inhibit driver is similar to the current sink in the EI driver, so I suspect the ID-2 module is being used to boost the current.  ↩

15. For reference, this footnote provides details of the Y driver signal routing. There are 8 high drive signals and 8 low drive signals generating the 64 Y select lines through the core stack. However, the current through the select line needs to go both ways, so cores can be flipped both directions. Thus, the drive signals are in pairs, one from the "E" side (voltage source) of the EI chip and one from the "I" side (current sink). These 32 signals go from the driver board to the diode matrix through two 16-wire flat cables. The diode board is connected to 64 Y select lines, but each line has two ends. These 128 connections are through four 32-wire flat cables, two on the left and two on the right. The two cables connected to the front side of the diode matrix wrap around to the far side of the stack, while the two cables connected to the back side of the diode matrix go to the near side of the stack. Thus, alternating select lines go through the stack in opposite directions. ↩

16. The X and Y diode matrices use a different wiring topology. There are 64 Y lines through the core stack. They are matrixed with 8 drivers at one end and 8 at the other end. The Y board has a diode pair (electrically) at each end of the 64 Y lines, so it has 256 diodes and 128 wires to the Y lines. (Because a line needs to be driven in either direction, one diode is required in each direction, making a pair at each end.)

    On the other hand, there are 128 X lines through the core stack, matrixed with 16 drivers at one end and 8 at the other end. To avoid doubling the number of diodes used, the X board only has a diode pair at one end of each of the 128 X lines. At the other end, groups of 8 X lines are tied together directly, forming 16 groups with one diode pair is used for each group. Thus, there are 256 diodes in the matrix, as well as 32 diodes associated with the 16 groups. As far as wires between the diode matrix and the core stack, there are 128 wires for the diode-connected end, and 32 wires corresponding to the grouped end. See Figures 10-42 and 10-43 in the Laboratory Maintenance Instructions for LVDC Vol. II (1965) for schematics.

    The X driver board is connected to other boards and the core stack through multiple flex cables. The cable on the right links the driver board to the rest of the computer via the I/O board. The top edge of the board has a 24-wire flex cable to the diode matrix, with a second 24-wire cable at the bottom. At the bottom, another smaller flex cable receives signals from the timing board underneath the core stack. The flex cables between the diode matrices and the core stack are not visible: there is a 16-wire cable and a 64-wire cable to the stack at the top and similar cables at the bottom.

    There is an important difference between the X and Y wiring. The four flat cables between the X diode matrix and the core planes went vertically, from the top and bottom of the matrix. The flat cables from the Y diode matrix went horizontally, from the sides of the matrix. In this way, the X and Y cables were attached to orthogonal sides of the core planes, connecting to the orthogonal X and Y wires. ↩

17. A special handle was produced to insert, remove, or carry the memory module. Because the memory modules were delicate and mounted with little clearance, this tool was developed to manipulate the module safely. This handle slides over the four shoulder screws on top of the module and latches into place.

    

    The special carrying handle for the memory module. From Laboratory Maintenance Instructions for LVDC Vol. II page 4-5.

     ↩

18. One interesting feature of the LVDC was that memory modules could be mirrored for reliability. In "duplex" mode, each word was stored in two memory modules. If one module had an error, the correct word could be retrieved from the other module. While this provided reliability, it cut the memory capacity in half. Alternatively, memory modules could be used in "simplex" mode, with each word stored once.

    Note that the LVDC's circuitry was triply-redundant to detect and correct errors. However, memory only needed to be doubly redundant because parity indicated which value was incorrect. The LVDC used odd parity. Odd parity had the advantage that parity would catch a word that was stuck all 0's or all 1's. One interesting feature of the simplex and duplex memory modes is that the software could switch between them while running, even setting separate modes for instructions and data. This allowed some words to be stored in simplex mode while more important words were stored in duplex mode. However, it appears that in actual use, the entire memory would be duplexed rather than specific parts. ↩

TROS: How IBM mainframes stored microcode in transformers

I recently came across a Transformer Read-Only Storage (TROS) module that stored microcode in an IBM System/360 mainframe computer. This unusual storage mechanism used a stack of Mylar sheets to hold 15,360 bits, equivalent to 1920 bytes. By modern standards, this is an absurdly small amount of data, but in 19641, semiconductor read-only memory chips weren't available, so using Mylar sheets for storage was a reasonable solution. In this blog post, I explain how the TROS module worked and its role in the success of the IBM System/360.

A TROS module, about 15" (39 cm) long. On the left, 60 transformers pass through the stack of 128 Mylar sheets. (Only the square ends of the transformers are visible.) The sheets are connected to the diode boards on the right. The TROS module is connected to the rest of the computer through the connector cables at the back.

How TROS worked: transformers and current pulses

The diagram below shows the concept behind TROS, simplified to two words of three bits each. The three transformers (square rings) each have a sense winding that generates one bit of output. Each word (A or B) has a drive line that passes either through a transformer (for a 1 bit) or around a transformer (for a 0 bit). In the diagram, drive line B (red) is activated by a current pulse. It generates a pulse (blue) from the second and third transformers, generating the bits 011 for Word B. The wiring for Word A, on the other hand, generates the bits 101. Storing more words is accomplished by threading more drive lines through (or around) the transformers, one for each word. Any bit pattern can be stored, depending on how the drive line is wired.

Simplified diagram of TROS storage. Based on Model 40 Functional Units.

The actual TROS module has 60 transformers and 256 drive lines, so it held 256 words of 60 bits. Physically threading 256 wires through transformers would be difficult, so the TROS module used a clever technique to make the wiring easy to assemble or modify. The wiring was printed on sheets of Mylar (called tapes), essentially a flexible printed circuit board. Each tape had two loops of wiring (called word lines) that either went through or around the transformers, so 128 Mylar tapes provided the wiring for 256 words.

A Mylar tape, holding 120 bits of data. It consists of two wire loops, connected to the four pins at the bottom.

The Mylar tapes were stacked on the 60 transformers as shown below. Each of the 60 transformers consisted of a U-shape with both arms passing through the stack of 128 tapes. In this way, the Mylar tapes efficiently created the wiring through and around the transformers, rather than threading individual wires.

Structure of the transformers, viewed from underneath. Each transformer consists of a U-piece that goes through the tapes, and an I-bar that completes the transformer. From Model 40 Functional Units.

Once the stack was complete, an I-bar was placed on top of each U to close the transformer core. A sense line (the reddish wiring below) was wrapped many times around each I-bar to detect the output signal. Each sense line was connected to a sense amplifier that detected the output signal, to produce the 60-bit output. (The I-bars and sense lines are missing from the TROS module I have but are visible in the module below.)

The sense windings are wrapped around the I-bars and connected to pins. The I-bars at the bottom are removed, showing the tops of the transformer U-pieces sticking up through the Mylar tapes. This TROS module is in the Computer History Museum.

The Mylar tapes were programmed by punching holes through wires to break the undesired wiring paths. The photo below shows a closeup of one of the tapes, showing the wiring printed on the tape, the large square holes for the transformer legs, and the small round holes punched through the word line wiring. The diagram on the right illustrates the wiring path resulting from the hole pattern. Each tape has two word lines (indicated in red and green) that go either through or around each transformer (gray rectangle).

Closeup of a TROS tape. The diagram on the right illustrates how the two traces (red and green) go through or around the transformers (gray rectangles), based on the holes punched in the tape.

To read one of the 256 words, one word line (wire loop) on one particular Mylar tape received a current pulse. The straightforward implementation would use 256 pulse drivers, with one selected by the address bits, but this much hardware would be expensive. Instead, the TROS module is driven by a "matrix" approach. The 256 word lines are wired logically into a 16×16 matrix. The address is split in half, and each half is decoded to select one of 16 lines. The word line that is selected on both ends line will receive a current pulse and be activated.2

Each Mylar tape is plugged into a diode board. Note the "2020" on the left, indicating that this module is from a System/360 Model 20.

Each Mylar tape is connected to one of two diode boards, resulting in hundreds of connections (above). (These diodes prevent the matrixed signals from all shorting together.) The diodes are inside the square aluminum modules below. The IBM System/360 didn't use integrated circuits, but instead used SLT modules, hybrid modules containing tiny semiconductors and thick film resistors. The SLT modules below each contain 8 diodes.

This closeup of the diode board shows the square metal SLT modules labeled 361485. Each one contains 8 diodes. The Mylar tape connections are at the top and bottom, while the "fin" in the middle is the wiring from the TROS module to the rest of the computer.

The TROS module I have was used on the low-end System/360 Model 20 computer, according to the label on it. The Model 20 was a slow, stripped-down system, lacking the full System/360 instruction set. Even so, its low cost ($1280 per month) made it the most popular System/360 model. The Model 20 contained 8 TROS modules, holding 6144 micro-instructions (3 micro-instructions per 60-bit word).3 These modules are visible on the left side of the computer below, mounted vertically. Note that the TROS modules take up a lot of space inside the computer.

IBM System/360 Model 20. TROS modules are on the left side. Photo from Ben Franske, CC BY 2.5.

In case you're wondering what the Model 20 microcode looks like, a sample is below. The microcode itself (in hex) is highlighted in blue, with the mnemonic expansion in green. Comments are on the right. The Model 20's microcode is much simpler than the horizontal microcode in larger System/360 systems.4

Microcode from the System 360/20. The micro-operations in the code are "Branch if Zero", "Add Immediate", "Branch if Plus", and "Branch if Minus", all acting on register R1. From FEMDM vol 2.

Why microcode?

One of the hardest parts of computer design is creating the control logic that tells each part of the processor what to do to carry out each instruction. In 1951, Maurice Wilkes came up with the idea of microcode: instead of building the control logic from complex logic gate circuitry, the control logic could be replaced with code (i.e. microcode) stored in a special memory called a control store. To execute an instruction, the computer internally executes several simpler micro-instructions, which are specified by the microcode. With microcode, building the processor's control logic becomes a programming task instead of a logic design task.

However, in the 1950s, storage technologies weren't fast and inexpensive enough to make microcode practical. It wasn't until the IBM System/360 (1964) that commercial computers made significant use of microcode. Microcode played a key role in the success of the System/360, helping IBM produce a line of computers with the same instruction set architecture but widely different implementations. Microcode also simplified backward compatibility, helping the System/360 support instruction sets of older IBM systems.5

IBM's various read-only storage techniques

IBM used several different read-only storage techniques to store microcode, for a combination of political and technical reasons. TROS was developed at IBM's Hursley site in England. This site started working on microcode because transistors were very expensive in England in the 1950s, and microcode could reduce the number of transistors required. Hursley developed a TROS for the SCAMP6 computer. This was followed by the TROS I've described, used on the System/360 Model 20 and Model 40, as well as the IBM 2841 file control unit.

A competing type of read-only storage is CCROS (Capacitive Coupled Read-Only Storage), which used Mylar sheets that functioned as a matrix of capacitors. An interesting feature of CCROS is that the Mylar sheets had the same size as an IBM punch card so microcode could be programmed by punching holes in it with a standard keypunch. CCROS was developed at IBM's Endicott site. Because the System/360 Model 30 was developed there too, it used the locally-developed CCROS even though CCROS was slower and less reliable than TROS. Each CCROS card holds 12 60-bit words. The Model 30 had 42 CCROS boards, each holding 8 cards, for a total of 4032 60-bit words.

Detail of a CCROS sheet. It is programmed by punching holes in it with a keypunch.

The high-performance Models 50, 65 and 67 required a faster control store, so they used a third technology, BCROS (Balanced Capacitor Read-Only Storage). Like CCROS, BCROS read bits by sensing capacitance, but BCROS used two capacitors for each bit (the Balanced Capacitors), which helped reduce noise and increased speed. The Mylar sheets for BCROS were 20″×8½″, much larger than the TROS and CCROS sheets. The data in BCROS was etched into the copper wiring (below), rather than by punching holes. Each bit is represented by two squares: one connected to the upper wire and one connected to the lower wire (or vice versa), forming the balanced capacitors. Each sheet plane held 176 words of 100 bits, and the system used 16 sheets to provide 2816 words.

Closeup of a BCROS sheet from a System/360 Model 50.

Instead of using special technology to store microcode, the low-end Model 25 held microcode in a 16-kilobyte section of core memory called Control Storage. In this model, different microcode was loaded from a card deck or tape to switch operating modes between System/360 and emulation of the legacy IBM 1400 series.

An important feature of these storage technologies is that the microcode could be easily updated at customer sites, by swapping the Mylar sheets (or card deck) holding the microcode. Many system bugs could be fixed inexpensively by changing the microcode. (In comparison, an "engineering change" on the older IBM 1401 typically required the engineer to modify wiring on the backplane, much more time-consuming and error-prone.) Microcode could also be upgraded if the customer purchased a new feature.

Comparison with core rope

TROS has some similarities with the core rope storage used by the Apollo Guidance Computer (AGC) to store programs, since both stored read-only data in the pattern of wires through cores. The tradeoffs were different between core rope and TROS. The AGC's core ropes were much more dense than TROS, an important feature for space flight. However, TROS could be easily changed by replacing the plastic tapes, while modifying a core rope required an expensive 8-week manufacturing process to wire up a new module.

Detail of core rope memory wiring from an early (Block I) Apollo Guidance Computer. Photo from Raytheon.

TROS and core rope are structurally the opposite, reversing the roles of word (address) lines and sense lines. TROS data depended on which word lines went through or around the transformer, while core rope data depended on which sense lines went through or around a core. To read a word in the AGC, one core was activated, while in TROS all of the transformers were (potentially) activated. Each transformer in TROS had one sense line and was associated with one output bit. In contrast, each core in the AGC's core rope had 192 sense lines and was associated with 12 words. (I've written more on core rope here).

Conclusion

TROS and other read-only storage technologies were a key ingredient in the overwhelming success of the IBM System/360 because they made microcode practical. However, the arrival of cheap semiconductor ROMs in the 1970s obsoleted complex storage technologies such as TROS. Nowadays, most microprocessors still use microcode, but it's stored in ROM inside the chip instead of in sheets of Mylar. Microcode can now be patched by downloading a file, rather than replacing Mylar sheets inside the computer.7

The TROS module, showing the diode boards and the stack of 128 Mylar tapes.

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Notes and References

1. The IBM System/360 was introduced in 1964. The date on this specific TROS module is May 27, 1970. ↩

2. The diagram below illustrates how the matrix selection and diodes work. This diagram has been simplified to 2 drivers, 4 gates, and 8 word lines; the real system has 16 drivers, 16 gates, and 256 word lines. (What IBM calls a "gate" here is not a logic gate, but a current sink forming the other end of the circuit.) By energizing a particular driver and gate pair, a word line is selected. For instance, if driver 1 and gate 3 are energized, word line 3 is selected, as shown in red. Note that without the diodes, signals could go backward, incorrectly energizing multiple word lines.

   ↩

   Matrix selection of a word line. Energizing driver DR1 and gate G3 selects word line W3. Based on Model 40 Functional Units, p61.

3. The Model 20 used 22-bit microcode words, so how did this work with 60-bit TROS? The trick was that some microcode words were truncated to 16 bits, so each TROS word held three microcode words: two 22-bit words, and one 16-bit word. In the Model 20's microcode, each word contained the address of the next microinstruction to execute. Since the truncated 16-bit word could only branch to a limited subset of next microinstructions. Thus, the microcode assembler had to carefully arrange the microcode so micro-instructions requiring a longer branch were stored in one of the longer 22-bit words. ↩

4. A 90-bit micro-instruction in the Model 50 could perform half a dozen different functions in parallel. For example, each yellow box below is a single micro-instructions that is part of floating-point multiplications. Each line in the box is a separate action; the micro-instruction can control the emitter, adder, shifter, mover, and local storage in parallel. The point is that the Model 50 was faster (in part) because it had multiple functional units, and the microcode needed to be much more complicated to control them.

   

   Two micro-instructions (in yellow) in the System/360 Model 50. This is part of the microcode to handle exponent underflow and overflow during floating-point multiplication. The black lines show control flow. The text outside the box is comments. From Model 50 diagram QG702

    ↩

5. Most System/360 computers used microcode because it reduced cost, increased flexibility, and made development faster. IBM imposed a rule that System/360 computers had to be implemented in microcode unless there was a very good reason not to. The fastest models used hardwired control circuitry, though, to maximize performance. ↩

6. Confusingly, IBM had two unrelated computers called SCAMP. The one using TROS is the Scientific Computer and Modulator Processor, a small computer developed at IBM Hursley for scientific applications, not the better-known prototype for the portable IBM 5100 (Special Computer APL Machine Portable). ↩

7. Modern x86 chips have hardcoded microcode, along with some SRAM that holds microcode patches to fix processor flaws. The patches are downloaded into the processor by the BIOS (details) after each power-on. ↩