Inside the die of Intel's 8087 coprocessor chip, root of modern floating point

Looking inside the Intel 8087, an early floating point chip, I noticed an interesting feature on the die: the substrate bias generation circuit. In this article I explain how this circuit is implemented, using analog and digital circuitry to create a negative voltage.

Intel introduced the 8087 chip in 1980 to improve floating-point performance on 8086/8088 computers such as the original IBM PC. Since early microprocessors were designed to operate on integers, arithmetic on floating point numbers was slow, and transcendental operations such as trig or logarithms were even worse. But the 8087 co-processor greatly improved floating point speed, up to 100 times faster. The 8087's architecture became part of later Intel processors, and the 8087's instructions are still a part of today's x86 desktop computers.1

I opened up an 8087 chip and took die photos with a microscope yielding the composite photo below. The die of the 8087 is fairly complex, with 40,000 transistors (according to Intel) or 45,000 transistors (according to Wikipedia). The photo shows the metal layer of the chip, the connections on top of the chip. The thickest white lines provide power and ground connections to all parts of the chip. Hidden underneath the metal are the polysilicon and silicon that form the chip's transistors. (Click the photo for a large image.)

Die photo of the Intel 8087 floating point coprocessor chip.

Die photo of the Intel 8087 floating point coprocessor chip.

The bottom half of the chip holds the 80 bit wide arithmetic circuitry: an adder, shifters, mathematical constant storage and registers. The large rectangle in the middle of the chip is the microcode that controls the chip. At the top is control logic and bus circuitry that interfaced with the 8086 processor. (I'll discuss the inner workings of the 8087 in more detail in later blog posts.)

The black lines around the outside of the die photo are the tiny bond wires connecting the pads on the die to the 40 pins of the chip. By studying the 8087 datasheet, it's not too hard to figure out which pad on the die corresponds to each pin of the chip; the chip's 40 pins (numbered counterclockwise) are wired in order to 40 pads on the chip. The diagram below zooms in on the center right part of the die, labeling some of the pads. (Note that the ground and +5V power (Vcc) pads have multiple wires in parallel to carry more current.) However, one puzzle appeared—an extra pad and wire located between pads 40 and 1, not associated with any of the chip's pins.

Each pad on the die of the 8087 FPU chip is wired to one of the 40 pins of the chip. But there is one extra wire between pins 1 and 40. It is connected to the chips's substrate.

Each pad on the die of the 8087 FPU chip is wired to one of the 40 pins of the chip. But there is one extra wire between pins 1 and 40. It is connected to the chips's substrate.

Looking at the bond wires on the chip (below) revealed that the mystery pad wasn't connected to one of the pins but to a tiny cubical block to the right of the die. Since the cube is on the same metallic base as the die, it connects to the die's underlying silicon, the substrate. I did some reverse-engineering and determined that this is part of the 8087's substrate bias circuit, which uses this connection to put a negative voltage on the substrate. The rest of this blog post explains how this circuit works.

The die of the 8087 FPU chip, showing the bond wires from the die to the package.

The die of the 8087 FPU chip, showing the bond wires from the die to the package.

What is substrate bias?

High-density integrated circuits in the 1970s were usually built from NMOS transistors. The diagram below shows the structure of an NMOS transistor. The integrated circuit starts with a silicon substrate, and transistors are built on this. Regions of the silicon are doped with impurities to create diffusion regions with desired properties. The transistor can be viewed as a switch, allowing current to flow between two diffusion regions called the source and drain. The transistor is controlled by the gate, made of a special type of silicon called polysilicon. A high signal voltage on the gate lets current flow between the source and drain, while a low signal voltage blocks current flow. An insulating oxide layer separates the gate from the silicon underneath; this insulating layer will be important later. These tiny transistors can be combined to form logic gates, the components of microprocessors and other digital chips.

Structure of a MOSFET as implemented in an integrated circuit.

Structure of a MOSFET as implemented in an integrated circuit.

For high-performance integrated circuits, it was beneficial to apply a negative "bias" voltage to the substrate. 2 To obtain this substrate bias voltage, many chips in the 1970s had an external pin that was connected to -5V.3 However, engineers didn't like chips that required an inconvenient extra voltage. Even worse, chips of that era often required a third voltage,4 so systems required three power supplies to support these chips. In addition, the number of pins on ICs was limited (typically just 18 pins for memory chips), so using up two pins for extra voltages was unfortunate. Part of the solution, developed around the end of the 1970s, was for chips to generate the negative bias voltage internally. The result was chips that used a single convenient +5V supply, making engineers happier.

Inside the 8087's substrate bias circuit

You might wonder how a chip can turn a positive voltage into a negative voltage. The answer is a circuit called the charge pump, which uses capacitors to generate the desired voltage.

The 8087's bias generator has two charge pumps working in alternation. The schematics below show the operation of one of the charge pumps. The charge pump is driven by an oscillating signal (Q) and its inverse (Q). In the first step, the upper transistor is switched on, causing the capacitor to charge to 5 volts with respect to ground. The second step is where the magic happens. The lower transistor turns on, connecting the high side of the capacitor to ground. Since the capacitor is still charged to 5 volts, the low side of the capacitor must now be at -5 volts, producing the desired negative voltage at the output. When the oscillator flips again, the upper transistor is turned on and the cycle repeats.5 The charge pump gets its name because it pumps charge from the output to ground. If you view the diodes as check valves, the charge pump is analogous to a manual water pump.

Schematic of the charge pump used in the Intel 8087 to provide negative substrate bias.

Schematic of the charge pump used in the Intel 8087 to provide negative substrate bias.

To reverse engineer the charge pump circuitry, I examined the die with a microscope. The metal layer obscures the transistors underneath, making it difficult to see the circuitry. But by dissolving the metal layer with hydrochloric acid, I exposed the polysilicon and silicon layers, revealing the transistors and capacitors, as seen below. (The colorful regions are simply interference patterns due to some oxide that wasn't fully removed.) The die photo below shows the two charge pumps: one to the left of the pad, and one below. Each charge pump matches the schematic above, with two diodes, a large capacitor, and two drive transistors.

The substrate bias circuit of the 8087. The metal layer has been removed in this die photo.

The substrate bias circuit of the 8087. The metal layer has been removed in this die photo.

The capacitors are the most visible feature of the substrate bias circuitry. Although microscopic, they are huge by chip standards. The area used by the capacitors is about the same as 72 bits of register storage, over 400 transistors. Each capacitor consists of polysilicon over a silicon region, separated by insulating oxide; the polysilicon and silicon form the plates of the capacitor. In the photo, the capacitors are studded with squares; these squares are contacts between the polysilicon or silicon and the metal layer on top. (The metal layer is not visible as it was removed.)

The four drive transistors are much larger than regular transistors since they must handle high current. The red lines are the polysilicon wires forming the gates. The green lines are contacts to the metal layer, connecting the transistors to +5V or ground. The diodes next to the pad are formed from transistors by connecting the gate and drain together (details).

The charge pumps are driven by the ring oscillator at the bottom of the above image. This ring oscillator consists of five inverters in a loop as shown below. Because the number of inverters is odd, the system is unstable and will oscillate. For instance, if the input to the first inverter is 0, the output from the fifth inverter will be 1. This will flip the first inverter, and the "flip" will travel through the loop causing oscillation. To slow down the oscillation rate, two resistor-capacitor networks are inserted into the ring. Since the capacitors will take some time to charge and discharge, the oscillations will be slowed, giving the charge pump time to operate.

The ring oscillator circuit in the 8087's charge pump.

The ring oscillator circuit in the 8087's charge pump.

Before explaining the ring oscillator, I'll show how a standard NMOS inverter is implemented in silicon. The diagram below shows an inverter, its schematic, and how it appears on the die. The inverter uses a transistor and a pull-up resistor (which is really a transistor). If the input is low, the transistor is off and the pull-up resistor pulls the output to +5V. If the input is high, the transistor is on, pulling the output to ground. Thus, the circuit inverts the input.

How an inverter is implemented with NMOS logic, and how it appears on the chip die.

How an inverter is implemented with NMOS logic, and how it appears on the chip die.

In the die photo above, the inverter's physical layout matches the schematic. The large beige regions are doped silicon. The thinner yellow areas bordered with purple are polysilicon. The input is a polysilicon wire. Where it crosses the doped silicon it forms the gate of a transistor between ground (below the input) and the output (above the input). The pull-up resistor is implemented with a transistor that has the gate and drain tied together; the indicated contact forms this connection between the transistor's polysilicon gate and its silicon drain. The polysilicon also forms the output wire. Thus, an inverter is implemented on the chip with two transistors.

The ring oscillator in the 8087 FPU chip, as seen on the die.

The ring oscillator in the 8087 FPU chip, as seen on the die.

The photo above shows how the ring oscillator appears on the die. The five inverters are outlined. Each inverter has a different orientation to optimize the layout, but careful examination shows the same transistor and pull-up structure explained above. The resistors and capacitors for the R-C delays are also indicated. The resistors are simply transistors with a long distance between source and drain, reducing the current flow. These capacitors are constructed like the charge pump capacitors, but are much smaller; the silicon on the bottom and the polysilicon on top form the capacitor plates, separated by the thin insulating oxide layer.

Conclusions

The substrate bias generator on the 8087 chip is an interesting combination of digital circuitry (a ring oscillator formed from inverters) and an analog charge pump. Substrate bias generator circuits were introduced in the late 1970s, helping memory chips and microprocessors to operate from a single +5V supply, much more convenient than requiring three different voltages. The substrate bias generator produces a negative voltage from the positive supply voltage by using a charge pump.

While the bias generator may seem like an obscure part of 1970s computer history, bias generation is still part of modern integrated circuits but has become much more complex, with multiple carefully regulated biases in multiple power domains. There is even a standard (IEEE 1801 power format) that allows IC design tools to generate the necessary circuitry.6

Likewise, even though Intel's 8087 floating point unit chip was introduced 38 years ago, it still has a large impact today. It spawned the IEEE 754 floating point standard used for most modern floating point arithmetic, and the 8087's instructions remain a part of the x86 processors used in most computers.

I'll end with one more 8087 die photo; this one shows the polysilicon and silicon after stripping off the metal. You may recognize the substrate bias generator circuit at the center right. (Click for a large image.)

Die photo of the Intel 8087 floating point unit. The metal layer has been stripped off with acid, revealing the polysilicon and silicon underneath.

Die photo of the Intel 8087 floating point unit. The metal layer has been stripped off with acid, revealing the polysilicon and silicon underneath.

I announce my latest blog posts on Twitter, so follow me at @kenshirriff for future 8087 articles. I also have an RSS feed. Thanks to Ed Spittles and Eric Smith for comments.

Notes and references

  1. The 8087 introduced a bunch of new instructions to the 8086, such as FADD (floating add), FDIV (floating divide) and FPTAN (tangent). These instructions were implemented using the 8086's ESC "escape" instruction, which was designed to let the 8086 processor interact with a coprocessor.

    The 8087 led to the IEEE 754 floating point standard in 1985; this defines the floating point used by most computers today. For more information on how the 8087 works, see The Intel 8087 numeric data processor by John Palmer or The 8087 Primer

  2. Putting a negative bias voltage on the substrate had several benefits. It decreased parasitic capacitance making the chip faster, made the transistor threshold voltage more predictable, and reduced leakage current

  3. Early DRAM memory chips and microprocessor chips often required three supplies: +5V (Vcc), +12V (Vdd) and -5V (Vbb) bias voltage. In the late 1970s, improvements in chip technology allowed a single supply to be used instead. For example, Mostek's MK4116 (a 16 kilobit DRAM from 1977) required three voltages while the improved MK4516 (1981) operated on a single +5V supply, simplifying hardware designs. (Amusingly, some of these chips still kept the Vbb and Vcc pins for backwards compatibility but left them unconnected.) Intel's memory chips followed a similar path, with the 2116 DRAM (16K, 1977) using three voltages and the improved 2118 (1979) using a single voltage. Similarly, the famous Intel 8080 microprocessor (1974) used enhancement-mode transistors and required three voltages. An improved version, the 8085 (1976), used depletion-mode transistors and was powered by a single +5V supply. The Motorola 6800 microprocessor (1974) used a different approach for a single supply; although the 6800 was built from the older enhancement-load transistors it avoided the +12 supply by implementing an on-chip voltage doubler, a charge pump that increased the voltage. 

  4. The third (+12V) supply in old chips is unrelated to the substrate bias. This supply was used because early MOS integrated circuits used enhancement-mode transistors as pull-up loads in gates. These transistors couldn't pull signals all the way up to the +5V level, so chips added an an even higher +12V supply. In the mid 1970's, new technology (ion implantation) allowed the creation of depletion-load transistors, which functioned much better as pull-up loads and eliminated the need for the +12V supply. For details, see Wikipedia, StackExchange and VLSI design techniques for analog and digital circuits page 539. 

  5. I've simplified the charge pump discussion slightly. Due to voltage drops in the transistors, the substrate voltage will probably be around -3V, not -5V. (If a chip requires a larger voltage drop, charge pump stages can be cascaded.) For the pump direction, I'm referring to current flow. If you think of it as pumping electrons, the negative electrons are being pumped the opposite direction, into the substrate. 

  6. Bias generators are now available as IP blocks that can be licensed and be plugged into a chip design. For more information on bias in modern chips, see Body bias, Multi bias domain implementation, or this presentation

Silicon die analysis: inside an op amp with interesting "butterfly" transistors

Some integrated circuits have very interesting dies under a microscope, like the chip below with designs that look kind of like butterflies. These patterns are special JFET input transistors that improved the chip's performance. This chip is a Texas Instruments TL084 quad op amp and the symmetry of the four op amps is visible in the photo. (You can also see four big irregular rectangular regions; these are capacitors to stabilize the op amps.) In this article, I describe these components and the other circuitry in the chip and explain how it works. This article also includes an interactive chip explorer that shows each schematic component on the die and explains what it does.

Die photo of the TL084 quad op amp. The bond wires got a bit bent while cleaning the chip.

Die photo of the TL084 quad op amp. The bond wires got a bit bent while cleaning the chip.

An integrated circuit consists of a tiny piece of silicon. To make an integrated circuit, regions are treated with various atoms to change the properties of the silicon, giving them different colors under a microscope. On top of the silicon, a thin layer of metal connects different parts of the chip. This metal is clearly visible in the photo as yellowish traces and regions. Under the metal, a thin, glassy silicon dioxide layer provides insulation between the metal and the silicon, except where contact holes in the silicon dioxide allow the metal to connect to the silicon. Around the edge of the chip, thin bond wires connect the metal pads to the chip's external pins.

NPN transistors inside the IC

Transistors are the key components in a chip. This op amp chip uses several types of transistors: NPN and PNP bipolar transistors as well as JFETs. (Many newer op amps use low-power CMOS transistors instead.) If you've studied electronics, you've probably seen a diagram of an NPN transistor like the one below, showing the collector (C), base (B), and emitter (E) of the transistor, The transistor is illustrated as a sandwich of P silicon in between two layers of N silicon; the N-P-N layers make an NPN transistor. It turns out that transistors on a chip look nothing like this, and the base often isn't even in the middle!

Symbol and simplified structure of an NPN transistor.

Symbol and simplified structure of an NPN transistor.

The photo below shows one of the transistors in the TL084 as it appears on the chip. The different brown, purple and green colors are regions of silicon that has been doped differently, forming areas called N and P regions (negative with an excess of electrons, and positive lacking electrons). The yellow areas are the metal layer of the chip on top of the silicon—these form the wires connected to the collector, emitter, and base. Underneath the photo is a cross-section drawing showing approximately how the transistor is constructed. There's a lot more going on than just the N-P-N sandwich you see in books, but if you look carefully at the vertical cross section below the 'E', you can find the N-P-N that forms the transistor. The emitter (E) wire is connected to N+ silicon. Below that is a P layer connected to the P+ base contact (B). And below that is an N layer connected (indirectly) to the collector (C).1

Structure of an NPN transistor in the TL084 op amp

Structure of an NPN transistor in the TL084 op amp

While most of the transistors follow the above pattern, some of the transistors in the TL084 chip are optimized in confusing ways, such as the part of the die below. In this circuit, two transistors share one collector (C), while a resistor (blue line) runs between them. (This took me a while to figure out, even with the schematic.)

A complex part of the TL084, where two transistors share a collector while a resistor runs through them.

A complex part of the TL084, where two transistors share a collector while a resistor runs through them.

The output transistors (below) in the TL084 are larger than the other transistors and have a different structure in order to produce the chip's high-current output. The output transistors must provide milliamps of current, compared to microamps for the internal transistors. Note the interlocking "fingers" of the emitter (E) and base (B), surrounded by the large collector (C). Although the NPN and PNP transistors look similar, the dark purple P silicon is visible on the base of the NPN transistor and the emitter and collector of the PNP transistor, showing their opposite construction.

High-current NPN and PNP transistors drive the output of the TL084 op amp

High-current NPN and PNP transistors drive the output of the TL084 op amp

How capacitors are implemented in silicon

The TL084 contains four capacitors to provide stability for the op amps. You can see the four capacitors in the die photo; they are the largest structures on the chip. A capacitor in the chip is essentially a large metal plate separated from the silicon by an insulating layer. The main drawback of capacitors on ICs is they are physically very large. The TL084's capacitors have a very small capacitance value (a few picofarads) but take up a large fraction of the chip's area.2

JFET transistors3

A special type of transistor called a JFET is the key to the high performance of the TL084 chip. The JFET transistor is related to the more common MOSFET transistor: they both controls current between the source and the drain, under control of the gate. But while the MOSFET has has an insulating oxide layer between the gate and the body of the device, the JFET lacks this layer and has a silicon P-N junction instead (and thus is called a Junction FET). The chip used P-channel JFETS, where current flows through a channel of P silicon; the schematic symbol and basic structure is shown below. Normally, current flows between the source (S) and drain (D) through the channel. As the voltage on the gate increases, it "pinches" the channel closed, reducing and then stopping the current flow. An important feature of a JFET is that very, very little current flows through the gate; the gate resistance is an amazingly large 1012Ω. (This is because the gate junction acts as a reverse-biased diode, blocking current flow.) This high input impedance is an important feature for an op amp.

Symbol and simplified structure of a JFET transistor (P-channel).

Symbol and simplified structure of a JFET transistor (P-channel).

On the chip, the JFETs are constructed like the diagram above but rotated horizontally. The diagram below shows a JFET as it appears on the die (left), along with a close-up slice. (The JFET channel is wide and snakes around in order to pass more current. It also has drains on both sides of the source.) The cross section below shows the internal structure of the JFET. The P region connects the source and the drain, and it is surrounded above and below by the gate's N region. (The connection to the lower N region is outside the region shown.) The JFETs in this chip are built with ion implantation, which shoots accelerated ions into the chip to produce the P and N regions. Ion implantation provides accurate control of the doping and dimensions of the P channel between the source and drain, allowing the input JFETs to be built for high performance.

Cross section of an input JFET transistor, showing the construction of the JFET.

Cross section of an input JFET transistor, showing the construction of the JFET.

Manufacturing JFET op amp ICs was difficult when they were first sold decades ago. Hybrid (two separate dies in one package) JFET op amps were introduced in 1970. These were followed shortly afterwards by monolithic (i.e. a single die) op amps, but difficulties in manufacturing consistent JFETs caused these op amps to have poor characteristics. In 1974, National Semiconductor engineers developed the ion implantation technique for fabricating consistent, high quality JFETs and used this "BIFET" technique to build better JFET op amps. Two years later Texas Instruments introduced their JFET op amps, including the TL084 which was the first four-in-one op amp using the BIFET process.4

You might have noticed that each op amp has four input JFETs on the die (forming the butterfly pattern below), even though the op amp only has two inputs. The explanation for this is that for good performance the input transistors in an op amps should have identical electrical characteristics. But unfortunately chips can have thermal gradients (i.e. hotter on one side than the other) that affect the transistor characteristics and unbalance the inputs. A standard solution used in the TL084 is that each input uses two cross-coupled transistors, diagonally opposite from each other. If one side of the chip is hotter than the other, both inputs will have an affected transistor, canceling out the effect of the temperature gradient.

To insure the input transistors are matched, each input transistor is actually two connected transistors, diagonally opposite. Wiring connects each transistor pair.

To insure the input transistors are matched, each input transistor is actually two connected transistors, diagonally opposite. Wiring connects each transistor pair.

IC component: The current mirror

There are some subcircuits that are very common in analog ICs, but may seem mysterious at first. Before explaining how the TL084 works, I'll first give a brief overview of the current mirror and differential pair circuits.

Schematic symbols for a current source.

Schematic symbols for a current source.

If you've looked at analog IC block diagrams, you may have seen the above symbols for a current source and wondered what a current source is and why you'd use one. The idea of a current source is you start with one known current and then you can "clone" multiple copies of the current with a simple transistor circuit.

The following circuit shows how a current mirror is implemented.5 A reference current passes through the transistor on the left. (In this case, the current is set by the resistor.) Since both transistors have the same emitter voltage and base voltage, they source the same current, so the current on the right matches the reference current on the left.

Current mirror circuit. The current on the right copies the current on the left.

Current mirror circuit. The current on the right copies the current on the left.

A common use of a current mirror is to replace pull-up resistors. Resistors inside ICs are both inconveniently large and inaccurate. It saves space to use a current mirror instead of a resistor whenever possible. Also, the currents produced by a current mirror are nearly identical, unlike the currents produced by two resistors.

IC component: The differential pair

The second important circuit to understand is the differential pair, the most common two-transistor subcircuit used in analog ICs.6 You may have wondered how the op amp subtracts two voltages since it's not obvious how to make a subtraction circuit. This is the job of the differential pair.

Schematic of a simple differential pair circuit. The current source sends a fixed current I through the differential pair. If the two inputs are equal, the current is split equally.

Schematic of a simple differential pair circuit. The current source sends a fixed current I through the differential pair. If the two inputs are equal, the current is split equally.

The schematic above shows a simple differential pair. The key is the current source at the top provides a fixed current I, which is split between the two input transistors. If the input voltages are equal, the current will be split equally into the two branches (I1 and I2). If one of the input voltages is a bit lower than the other, the corresponding transistor will conduct more current, so one branch gets more current and the other branch gets less. As one input continues to increase, more current gets pulled into that branch. Thus, the differential pair is a surprisingly simple circuit that routes current based on the difference in input voltages. The TL084 uses JFETS instead of bipolar transistors in the differential pair, but the principle is the same.

The internal blocks of the op amp

The internal circuitry of the TL084 op amp is similar to the 741 op amp, which has been explained in many places7, so I'll just give a brief description of the main blocks. The interactive chip viewer below provides more explanation.

The two input pins are connected to the differential amplifier, which is based on the differential pair described above. The output from the differential amplifier goes to the second (gain) stage, which provides additional amplification of the signal. Finally, the output stage has large transistors to generate the high-current output, which is fed to the output pin. The capacitor stabilizes the op amp to avoid oscillation. The current mirror at the top provides currents to other parts of the chip. The current mirror at the bottom functions as an active load increasing the gain of the differential pair.

Die for the TL084 op amp, showing the main functional units.

Die for the TL084 op amp, showing the main functional units.

Interactive chip viewer

The image and schematic8 below are an interactive exploration of the TL084. Click a component to see its location on the die and in the schematic highlighted. The box below will give an explanation of the component. The die image below shows one of the four op amps on the chip; the others are essentially identical.

Click components in the image below for more information.

How I photographed the die

Getting to the die of an integrated circuit can be difficult since integrated circuit usually come in a black epoxy package. I'd rather avoid using dangerous concentrated acid to dissolve the epoxy package and see the die. Fortunately some ICs, such as the TL084, are available in ceramic packages that can be easily opened with a chisel. The photo below shows the chip package after removing the lid. The four large capacitors are visible on the die even without a microscope.

The TL084 op amp. The ceramic package has been opened, exposing the die inside. A couple pins fell off when the package was opened.

The TL084 op amp. The ceramic package has been opened, exposing the die inside. A couple pins fell off when the package was opened.

To obtain the die photos, I used a metallurgical microscope, which shines light from above through the lens, unlike a normal microscope which shines light from below. A metallurgical microscope is the secret to getting clear photos at higher magnification, since the die is brightly illuminated. I used Hugin to stitch multiple images together into high-resolution pictures. Below is a second die photo; the bond wires are removed in this one.

Die photo of the TL084 op amp with the bond wires removed.

Die photo of the TL084 op amp with the bond wires removed.

Conclusions

Texas Instruments introduced the TL084 in 1976 as one of the first high-performance quad op amps. I was motivated to study this chip by the pretty butterfly-like patterns on the die, but found some interesting circuitry inside the chip. The butterfly-like structures turned out to be JFET transistors that improved the chip's performance by providing high impedance for the op amp inputs. If you enjoyed this look inside an analog silicon chip, you may also like my analysis of the 741 op amp and 555 timer. Follow me on Twitter at @kenshirriff for my latest blog posts, or use my RSS feed. The chip was provided by Eric Schlaepfer (@TubeTimeUS).

Notes and references

  1. You might have wondered why there is a distinction between the collector and emitter of a transistor, when the simple picture of a transistor is totally symmetrical. Both connect to an N layer, so why does it matter? As you can see from the die photo, the collector and emitter are very different in a real transistor. In addition to the very large size difference, the silicon doping is different. The result is a transistor will have poor gain if the collector and emitter are swapped. 

  2. The capacitor in the op amp is located at a special point in the circuit where the effect of the capacitance is amplified due to something called the Miller effect. This allows the capacitor to be much smaller than it would be otherwise. Given how much of the die is used for the capacitor already, taking advantage of the Miller effect is very important. 

  3. Yes, I realize that "JFET transistor" is a redundant acronym. Since some readers may not be familiar with JFETs, I want to remind them that JFETs are transistors. 

  4. For an extremely detailed history of op amps, including the development of JFET op amps in the 1970s, see Op Amp History by Walt Jung. My section on JFET op amp history is based on this source. 

  5. For more information about current mirrors, you can check Wikipedia or chapter 3 of Designing Analog Chips. If you're interested in how analog chips work, I strongly recommend you take a look at Designing Analog Chips. 

  6. Differential pairs are also called long-tailed pairs. According to Analysis and Design of Analog Integrated Circuits differential pairs are "perhaps the most widely used two-transistor subcircuits in monolithic analog circuits." (p214) For more information about differential pairs, see Wikipedia, any analog IC book, or chapter 4 of Designing Analog Chips

  7. The TL084 op amp's design is similar to the 741 op amp, which is described in Wikipedia, Operational Amplifiers, IC Op-Amps Through the Ages and UNCC class notes. See any of those sources for more details on how op amps are constructed. 

  8. The schematic is from the TL084 datasheet

Inside the 76477 Space Invaders sound effect chip: digital logic implemented with I2L

The 76477 Complex Sound Generation chip (1978) provided sound effects for Space Invaders1 and many other video games. It was also a popular hobbyist chip, easy to experiment with and available at Radio Shack. I reverse-engineered the chip from die photos and found some interesting digital circuitry inside. Perhaps the most interesting is a shift register based white noise generator, useful for drums, gunshots, explosions and other similar sound effects. The chip also uses a digital mixer to combine the chip's different sound generators. An unusual feature of the chip is that it uses Integrated Injection Logic (I2L), a type of digital logic developed in the 1970s with the goal of high-density, high-speed chips. (I wrote about the chip's analog circuitry last year in this article.)

Functionality blocks inside the 76477 sound chip, indicated on the die. Die photo courtesy of Sean Riddle.

Functionality blocks inside the 76477 sound chip, indicated on the die. Die photo courtesy of Sean Riddle.

Looking under a microscope, you can see the circuitry that makes up the chip. The yellowish lines above are the metal traces that connect the circuits of the die. The reddish and greenish regions are the silicon of the chip, forming transistors and resistors. The black blobs around the edges show where tiny bond wires connected the die to the integrated circuit pins. I've outlined the analog circuits outlined in purple, while digital circuits are in cyan. The 76477 is primarily analog—most control signals are analog, the chip doesn't have digital control registers, and most sounds are generated from analog circuits—but about a third of the chip's area is digital logic.

The block diagram below shows the 76477 chip's functional elements and can be compared to the die photo above. The voltage-controlled oscillator (VCO) produced a tone whose frequency depends on the control voltage. The "super low frequency" SLF oscillator generated a triangle wave. Feeding this into the VCO generated a varying pitch, useful for bird chirps, sirens, or the warbling sound of the UFO in Space Invaders. The "one-shot" produced a pulse of a fixed length to control the length of the sound. The envelope generator made the sound more realistic by ramping its volume up at the start (attack) and down at the end (decay). The digital white noise generator was used for drums, gunshots, explosions and other similar sound effects. Finally the digital mixer combined these signals and fed them to the output amplifier.

Block diagram of the 76477 sound chip, from the datasheet. Digital inputs: triangles, resistor inputs: red, capacitor inputs: cyan, voltage inputs: violet.

Block diagram of the 76477 sound chip, from the datasheet. Digital inputs: triangles, resistor inputs: red, capacitor inputs: cyan, voltage inputs: violet.

The remainder of this article will dive into how the digital circuitry of the 76477 chip was implemented. First I'll explain Integrated Injection Logic (I2L), a short-lived logic family that was supposed to revolutionize computer chips. Next, the noise generator, control logic and the digital mixer are reverse engineered and explained.

Integrated Injection Logic

You may be familiar with TTL integrated circuits, such as the popular 7400 family. These chips are built from bipolar transistors—NPN and PNP transistors—and were fast. (Minicomputers were built from boards full of TTL chips, taking advantage of its speed.) Unfortunately, TTL gates required multiple transistors and bulky resistors, so it was difficult to fit a lot of TTL circuitry into an integrated circuit. The die photo below illustrates the complexity of a single TTL inverter. (For details on how it works, see my earlier post.)

Die photo of a TTL inverter. The inverter uses four transistors, four resistors and two diodes.

Die photo of a TTL inverter. The inverter uses four transistors, four resistors and two diodes.

A competitor to TTL was MOS; in the early 1970s, integrated circuits based on MOS transistors led to the rise of the microprocessor. Unlike TTL, MOS transistors could be densely crammed onto VLSI integrated circuits, but unfortunately, MOS was much slower than TTL. This posed a dilemma in the 1970s: TTL couldn't implement dense circuitry and MOS was too slow. The integrated circuit industry needed a technology that combined the speed of TTL with the density of MOS, and it looked like I2L was the solution. (Spoiler: I2L wasn't the wave of the future; CMOS was.)

I2L solved the problems of TTL and MOS with a clever new design. Each I2L gate was built from a single multi-collector bipolar transistor instead of the multiple transistors of TTL. Even better, the transistors could be arranged in a high-density grid. Finally, the bulky resistors of TTL were replaced by an "injector", a tiny transistor that injected the necessary current. For a final bonus, I2L was compatible with existing silicon fabrication techniques and could be built on the same chip with bipolar analog circuitry. (This was important for the 76477 sound chip, which combined analog and digital circuits on one chip.) In the late 1970s and early 1980s, I2L looked like the dream technology that would take over the integrated circuit industry. A variety of I2L chips were built, including digital watch chips and some microprocessors, as well as the 76477 sound chip.

The diagram below shows six logic gates on the 76477, implemented with I2L logic. There are two columns of gates, with injectors down the middle. Each gate consists of one transistor (inner green rectangles). Note the high density of the circuitry, without wasted space. Each I2L gate is implemented with a single transistor, compared to multiple transistors and bulky resistors for a single TTL gate (compare with the TTL photo above). Unlike TTL, which requires considerable wiring inside a gate, I2L only uses wiring between gates. (Gates are connected by a layer of metal, which appears as thick yellow lines in the die photos.)

Six I2L gates in the 76477 chip. Each gate is implemented with a single, compact transistor.

Six I2L gates in the 76477 chip. Each gate is implemented with a single, compact transistor.

I2L is a bit tricky to understand; it's like being in a crazy backwards world compared to TTL. A normal logic gate (such as a NAND gate) has a few inputs and one output. But an I2L gate has one input and multiple outputs! How can that work? The schematic below shows an I2L gate, with one input and three outputs. Normally the current from the injector (ICC) turns on the output transistor, pulling the output low. But if the input is low, the output transistor turns off and the output will be high.2 Thus, the gate inverts the input. (You can think of the injector as a pull-up resistor on the input.)

Implementation of a I2L gate. Note that it has a single input and multiple outputs. Icc is the injected current. From "Integrated Injection Logic: A Bipolar LSI Technique".

Implementation of a I2L gate. Note that it has a single input and multiple outputs. Icc is the injected current. From "Integrated Injection Logic: A Bipolar LSI Technique".

Since the circuit above has a single input, it may seem to be just an inverter. But by wiring several signals together at the input, you get an AND gate "for free": if any signal is low, it will pull the wire low, and otherwise the signal is high. This is called "wired-AND". The wired-AND input to the I2L inverter results in a NAND gate.

One problem arises with wired-AND: if you connect an output to more than one wired-AND, everything gets shorted together. The solution is to have multiple outputs from the inverter. Thus, each I2L NAND gate has a single input and multiple identical outputs. The outputs from various gates (A and B below) are connected together and fed to the input of a I2L gate, creating a NAND gate.

Diagram of a NAND gate implemented in Integrated Injection Logic (I2L). From "Integrated Injection Logic: A Bipolar LSI Technique".

Diagram of a NAND gate implemented in Integrated Injection Logic (I2L). From "Integrated Injection Logic: A Bipolar LSI Technique".

Compared to TTL, I2L is also constructed "backwards". The transistors in I2L have multiple collectors, while the transistors in TTL have multiple emitters.3 It may seem strange to think of transistors with multiple collectors, but the diagram below shows how they are constructed. Each collector has an N region (brown) with a P region (green) below for the base, and another N region at the bottom, forming an NPN transistor. The multiple collector is built by creating multiple N regions. Note that the transistor's emitter is the grounded substrate. Also note that the injector PNP transistor is just a P region, reusing the emitter and base's N and P regions; this make the injector more compact than a "full" transistor.

Die photo and cross section diagram of an I2L gate in the 76477 sound effects chip. The transistor base, collectors, and emitters are labeled along with the current injection.

Die photo and cross section diagram of an I2L gate in the 76477 sound effects chip. The transistor base, collectors, and emitters are labeled along with the current injection.

Noise generator

The 76477 generates sounds such as a gunshot, explosion, steam train, or drum by producing a burst of white noise, a hissing staticky sound. Although white noise is relatively difficult to generate with an analog circuit, it can be simulated by a digital shift register circuit.5 Linear feedback shift registers are a well-known technique, generating each new bit by combining some of the existing bits with an exclusive-or operation. With a careful design, a LFSR with an n-bit shift register can output 2^n-1 pseudorandom bits before repeating. The 76477, however, uses a nonlinear feedback shift register, a less-known technique that uses a different function to generate new bits.

The output from the noise shift register is a pseudorandom sequence of 0's and 1's, output at the shift register's clock frequency. The oscilloscope trace below shows the output sequence.

Random noise output form 76477 sound chip.

Random noise output form 76477 sound chip.

The shift register consists of 32 stages, each built from a two-latch flip flop.8 Looking at the die, we can see the shift register and determine the function that generates new bits. Bits move through the shift register as indicated by the white arrow. The feedback logic generates each new input bit from the current bits.7 The output is a pseudo-random bit that repeats after 56883 cycles.6

Die photo of the shift register white noise generator in the 76477 sound effects chip.

Die photo of the shift register white noise generator in the 76477 sound effects chip.

The noise circuitry is driven by a clock signal, either external or internal. The internal clock is produced by a ring oscillator consisting of 15 inverters wired in a loop. Because the number of inverters is odd, the input signal will be inverted after it goes through the loop and reaches the input. Thus, the circuit will continuously oscillate.

The noise shift register is driven by a clock generated from fifteen inverters forming a ring oscillator.

The noise shift register is driven by a clock generated from fifteen inverters forming a ring oscillator.

The die photo above shows the structure of the ring oscillator. Each inverter is connected to the next, as indicated by the white arrow. The last inverter is connected to the first through the "ring feedback" wire. The output from the ring oscillator is a bit unusual, due to the single-input multi-output structure of I2L. The output is tapped from the third inverter, which has a second output. It is connected to a 4-output inverter, which drives the four output inverters in parallel. This produces an output with four times the regular current, sufficient to drive the shift register.

The noise filter

The sound of the noise can be tuned for different effects such as a high-pitched gunshot or a lower-pitched steam engine. This filtering is done by the noise filter, an adjustable low-pass filter that processes the pseudo-random white noise produced by the shift register. While this circuit is analog, I'll explain it here since it's part of the noise circuitry. The filter is basically an integrator, controlled by an external resistor and capacitor. In other words, the filter converts the sharp pulses from the shift register into ramps up or down, for inputs of 1 or 0 respectively, yielding the waveform below. (A slower ramp up and down yields an output signal that changes more slowly and is biased towards low frequencies, filtering out more high frequencies.) This signal is then converted back into a digital signal, which is used as the noise signal by the rest of the chip.

Random noise output form 76477 sound chip after filtering and before conversion back to digital pulses.

Random noise output form 76477 sound chip after filtering and before conversion back to digital pulses.

On the die, the noise filter is made of NPN and PNP transistors, along with some resistors (long red squiggles). You can see that analog circuits are not as dense as the I2L transistors. The black blobs are where bond wires connect the die to the IC pins.

The noise filter circuitry is next to the shift register on the die. It is an analog circuit, built from NPN and PNP transistors.

The noise filter circuitry is next to the shift register on the die. It is an analog circuit, built from NPN and PNP transistors.

While the noise filter is controlled by an external resistor and capacitor, it is built very differently from a typical R-C filter. The schematic (below) shows that the noise filter is built largely from current mirrors. (A current mirror is a controllable current sources built from a few transistors, shown as an arrow in a circle on the schematic.) The external resistor sets the current through the current mirror reference. Under the control of the shift register output, the double current mirror (two arrows) will either sink twice the resistor current or nothing. Summing the two currents yields either a charging current or a discharging current for the capacitor, equal to the resistor current. The result is the external capacitor will be charged or discharged with a steady current, with the rate controlled by the external resistor. Finally, the capacitor voltage is converted to a clean digital output by a Schmitt trigger, and fed to the mixer. The chip uses this current mirror "trick" in multiple places and I've written about it here if the description here is too brief.

Schematic of the noise filter. This low-pass filter integrates the input signal, using multiple current mirrors (arrow symbol). The frequency response is controlled by the external resistor and capacitor.

Schematic of the noise filter. This low-pass filter integrates the input signal, using multiple current mirrors (arrow symbol). The frequency response is controlled by the external resistor and capacitor.

Miscellaneous logic

There's a block of I2L circuitry that implements miscellaneous digital logic to control the chip. It implements the envelope select logic that generates the attack and decay signals that shape the output sound.11 This logic block also processes the inhibit and reset inputs, used to produce bursts of sound. I won't go into the details of this logic; it's basically NAND gates, inverter buffers, and a T flip flop built from NAND gates. The die photo below shows the efficient, dense packing of I2L logic; each column contains two gates.

Miscellaneous logic circuits in the 76477 sound effects chip.

Miscellaneous logic circuits in the 76477 sound effects chip.

The mixer

The 76477 includes a mixer that allows any combination of the three sound sources (Voltage-Controlled Oscillator, Super-Low Frequency oscillator, and noise) to be combined to form the output. The mixer isn't an analog mixer, but just ANDs together the digital inputs. Unfortunately this makes the mixer less useful since inputs aren't combined as audio sounds, but essentially gate each other.

The three mixer input pins select which sound sources are combined to form the output.

The three mixer input pins select which sound sources are combined to form the output.

The mixer is implemented by an 8-input multiplexer, consisting of eight NAND gates feeding an output NAND gate (below).13 Each gate is enabled by one of the eight mixer select combinations (above), and passes the corresponding sound signals. Finally the 8-input NAND gate merges the eight branches to produce the output.12 For instance if A, B and C are low (selecting VCO), the top NAND gate is active, passing the VCO signal to the output. If A is high, B is low and C is high, the SLF, VCO and Noise signals are ANDed and passed to the output. If A, B and C are all high (Inhibit), the bottom gate pulls the output high. The logic is essentially a direct implementation of the table above.

Schematic of the mixer, showing three of the eight multiplexer gates.

Schematic of the mixer, showing three of the eight multiplexer gates.

The die photo below shows the mixer. The black line indicates the middle NAND gate, which on the die has a single input and a single output. The key point is that with I2L, a 6-input NAND gate is implemented by wiring together the 6 desired signals to a single gate input. This wire is indicated in blue with the 6 desired input signals marked with blue circles. Likewise, the eight NAND gate outputs (red circles) are wired together (red line) for the output. Interpreting an I2L circuit is confusing because of the conceptual reversal of inputs and outputs.

Die photo showing the digital mixer in the 76477 sound effects chip.

Die photo showing the digital mixer in the 76477 sound effects chip.

Conclusions

In the late 1970s, I2L was heralded as the technology of the future, combining the speed of TTL integrated circuits with the density of MOS.9 I2L reached its peak with the production of 16-bit microprocessors by Fairchild and Texas Instruments in the 1970s and 1980s.14 Fairchild's I2L Microflame processors lived up to their name, running so hot that some chips were packaged on beryllium oxide, a toxic ceramic that conducts heat better than most metals. Unfortunately for I2L, CMOS turned out to be the winning technology. CMOS's extremely low power consumption and scalability allowed CMOS chips to hold exponentially more circuitry (as described by Moore's Law) making modern microprocessors possible. Thus, the processor you're using now is built from CMOS and I2L is a historical footnote.

The 76477 sound chip is an unusual combination of analog and digital circuitry, using I2L for the digital logic. Since the sound chip was primarily controlled by resistors, capacitors and voltages, it was difficult to control with a microprocessor. As a result, the 76477 sound chip was soon overshadowed by digital sound chips, such as the AY-3-8910 and the 76489 that could easily be interfaced to a microprocessor.15 Nevertheless, the 76477 chip was popular with hobbyists as it was easy to experiment with and readily available at Radio Shack. Although long obsolete, the 76477 still lives on in the occasional retro project and (inexplicably) an iPhone app.

The 76477 sound chip was popular with hobbyists and sold at Radio Shack. Photo courtesy of Bill Lewis.

The 76477 sound chip was popular with hobbyists and sold at Radio Shack. Photo courtesy of Bill Lewis.

I announce my latest blog posts on Twitter, so follow me at kenshirriff. I also have an RSS feed. Thanks to Sean Riddle for the die photos.

Notes and references

  1. The Space Invaders schematics show that the video game used seven different circuits to create its different sounds. The 76477 generated the "UFO" sound, while other sounds (saucer hit, explosion, missile, invader hit, etc.) were mostly generated by collections of op amps. 

  2. In the I2L schematic as shown, the output will be floating when not pulled to ground. But in use, the output will be connected to another gate, and its injector current will pull the output high. 

  3. If you're familiar with TTL circuitry, you may know that it uses transistors with multiple emitters. The multiple-collector transistors used by I2L are constructed in essentially the same way on die, except the role of the emitter and the collector are swapped. 

  4. When looking at the 76477 die, a collector and a base are almost identical, which I didn't expect. Fortunately, there is a subtle difference that lets you distinguish them: both have a circle inside a square, but for some reason the base's circle touches the square while the collector's circle is centered. 

  5. Because the output of the shift register is pulses at a fixed clock frequency, the noise isn't "genuine" white noise, which has a flat frequency spectrum and is more random. However, the shift register output is a reasonable approximation below the clock frequency. Some discussion is here

  6. The pseudo-random noise output from the shift register repeats after 56883 cycles. This is much worse than you could get from a 32-bit LFSR (a cycle of length 2^32-1), so they could have used a much smaller shift register. Perhaps the nonlinear terms help initialize the shift register; a linear-feedback shift register can get stuck in the all-zeros state. 

  7. The nonlinear feedback function is NOT ((r2 XOR r30) OR (r2 AND r26 AND r27 AND r28 AND r29 AND r30)). I verified that the chip's output matches this formula. Interestingly, the Mame emulator's code for the 76477 uses a similar, but not identical noise algorithm. 

  8. One puzzling feature of the shift register is that there is no wiring between the stages! How do bits get from one stage to the next? Did the chip have another layer of wiring that wasn't in the photos? Was there some sort of hidden connection? Eventually I noticed that there wasn't an isolation ring between the stages—a silicon barrier that separated most I2L circuits. Without this isolation ring, an "invisible" PNP transistor exists between the stages, apparently allowing one stage to flip the next stage to the right value. Each shift-register stage is constructed from two NAND-gate latches. When the clock is low, the first latch is forced into an indeterminate state. When the clock goes high, the latch ends up as 0 or 1 based on the bias it receives from the previous stage through the "invisible" PNP transistors. Thus, the latch becomes edge-sensitive since it will change right on the clock's rising edge. I found a paper ("Injection-Coupled Synchronous Logic", 1978) that describes a similar technique for an I2L shift register9, so I think this is the right explanation, even though the circuit seems a bit sketchy. 

  9. See the 1976 article "Integrated Injection Logic: A Bipolar LSI Technique"for an overview of I2L (pdf). The most thorough reference I've found on I2L is the book Integrated Injection Logic (1980), a collection of dozens of articles on I2L.  

  10. The die has a multi-transistor circuit connecting the env1 pin to the shift register. It looks like pulling the env1 input above 5 volts should reset the shift register. Perhaps this is an undocumented feature for testing. However, I couldn't make this work on an actual chip, so it's a bit mysterious. 

  11. Strangely, the envelope control logic has separate logic to generate the attack and decay signals, even though they are simply complements of each other. I wonder if the designers originally planned a more complex envelope, perhaps attack, sustain, and decay. 

  12. The mixer implementation can be viewed as AND gates feeding an OR gate (rather than NAND gates feeding a NAND gate). This follows from De Morgan's Law

  13. The mixer implementation is more complex than it needed to be for no apparent reason. An easier approach would be to have each mixer select input control one of the three signals with a simple NAND gate. Instead the mixer options are ordered apparently randomly, requiring the complex multiplexer. 

  14. I'll give a brief summary of I2L microprocessors. Fairchild's Microflame architecture series started with the 16-bit F9440 processor in 1977. (The Microflame processors used Fairchild's "Isoplanar Integrated Injection Logic" technology (I3L); presumably this was one better than regular I2L.) The Fairchild F9445 microprocessor (1979) implemented the architecture of the Data General Nova minicomputer. In 1980 the US Air Force came up with a standard 16-bit processor architecture called MIL-STD-1750A and multiple companies built microprocessors meeting this standard. Fairchild's I2L entry in this market was the F9450. Meanwhile, Texas Instruments produced the 4-bit SBP0400 bit-slice processor (1975) with 1660 gates. This was followed by I2L processors in its 16-bit 9900 family: the SBP9900 with 6034 gates (1979) and improved SBP9989 with 5000 gates (1981). I2L processors were used in the niche market of radiation-resistant processors for space applications. For example, the TI SBR9000 (1985), a successor to the 9900. One radiation-resistant I2L microprocessor was the TI SBR9000 

  15. The 76477 has a few design decisions that don't make sense to me. One is the complex, suboptimal shift register configuration for the noise generator. Another is the digital mixer configuration that makes the mixer circuit unnecessarily complex. Finally, the envelope control logic seems like it was designed for more complex envelopes than than the chip actually implemented. I don't like to criticize chip designs, figuring the designers must have known what they were doing, but I have to wonder about the 76477.