Details about 8085 registers

This page contains additional information about the 8085 registers that didn't fit in my main discussion. This page probably won't make much sense on its own, so if you ended up here somehow, I recommend The 8085's register file reverse engineered instead.

Stepping through the LXI instruction

To understand this table, a bit of background on 8085 instruction timing. An instruction cycle is broken down into one or more M (machine cycles), where an 8-bit memory access can be done in one M cycle. Each M cycle is broken down into several T-states, where each T-state corresponds to one clock cycle. Each clock cycle has a low phase and a high phase.

The following table illustrates execution of an LXI D, d16 instruction that loads the DE register pair immediately with the following two bytes. The instruction takes three M cycles, one to fetch the opcode and two to fetch the data bytes. The data bytes are moved into the registers via the ALU. Data movement is carefully arranged so the PC operations and register operations don't collide. Instruction execution is overlapped with the fetch of the next instruction; the D register is loaded in T3 of the next instruction.

cycle	T/clock	PC action	Register action
	T3/0
	T3/1	PC → inc latch
M1 opcode fetch	T1/0	inc latch → address pins
	T1/1	inc latch → address pins
	T2/0
	T2/1	inc → PC
	T3/0		data pins → dbus → instruction reg
	T3/1
	T4/0
	T4/1	PC → inc latch
M2	T1/0	inc latch → address pins
	T1/1	inc latch → address pins
	T2/0
	T2/1	inc → PC
	T3/0		data pins → dbus → TMP reg
	T3/1	PC → inc latch
M3	T1/0	inc latch → address pins
	T1/1	inc latch → address pins	ALU → dbus → E reg
	T2/0
	T2/1	inc → PC
	T3/0		data pins → dbus → TMP reg
	T3/1	PC → inc latch
M1 opcode fetch	T1/0	inc latch → address pins
	T1/1	inc latch → address pins
	T2/0
	T2/1	inc → PC
	T3/0		data pins → dbus → instruction reg
	T3/1		ALU → dbus → D reg
	T4/0
	T4/1	PC → inc latch

Register amplification

To read a register value and output it to the data bus requires an amplification circuit, which is considerably more complex than the simple driver circuit I'd expect.

Most of the time, MOSFETS can be viewed as simple switches. However, the amplification circuit depends on careful sizing of the transistors. This ensures the right value when two transistors pull a wire in conflicting signals. Making these transistors low-current also ensures that such a "short circuit" doesn't result in too much current flow. Such circuits mean a simple transistor-level simulator won't work for the 8085, and a simulator must take transistor sizes into account. The schematic below shows the "strength" (i.e. current capacity) of the various transistors in the amplifier/driver circuit.

Starting at the bottom, if both inputs are high, all four input transistors will conduct, causing a short circuit. However, since the current capacity of these transistors is very low, the short circuit is not a problem. In addition, since the pulldown transistors are stronger than the pullup transistors, both outputs will be low, rather than an indeterminate value. This ensures that the group of four transistors in the middle will not all conduct at the same time. However, if /lreg_rd is high (i.e. output disabled), a short circuit can occur with these transistors, since they can output high while the /lreg_rd transistors pull the output low. Again, the pullup transistors are weak, so the short circuit won't cause excessive current, and the lines will be pulled low. Finally, the two transistors at the top are very high current transistors, to drive the long, high-capacitance data bus. However, the previous circuitry ensures they will not both conduct at the same time.

The current capacity of the transistors is controlled by their W/L ratio. The key parameter in the performance of a MOSFET transistor is the width to length ratio of the gate. The current provided by the transistors is proportional to this ratio. (Width is the width of the source or drain, and length is the length across the gate from source to drain.) (See Introduction to VLSI Systems, Mead, Conway, p 8.) To oversimplify, a transistor with a wide source and drain and a snaking gate is high-current, while a blocky square transistor is low-current.

Schematic of the amplifier/driver to read one bit of the register file to the data bus.

The circuit to amplify the register bus for use by the address latch is much simpler, since the address latch is much easier to drive (requires less current).

Schematic of the 8085's amplifier to read one bit of the register file into the address latch.

Register select schematic

Schematic of the 8085 circuit to use the appropriate three register select bits. Multiplexers select either the lower three bits or the next three bits from the instruction stored in the instruction register. The flip flop defaults to the middle three bits unless control line RC_14 indicates it's the right operation and time to look at the lower three bits (generally a MOV instruction.

Octal table.

XCHG circuit schematic

The following circuit handles exchanges of the DE and HL registers. The RC_15 control line indicates a XCHG instruction and toggles the flip flop. The upper AND-NOR gate detects a DE operation (01x register code) while the lower AND-NOR detects a HL operation (10x register code). Control line RC_09 indicates the register bits from the instruction should select the register, while RC_10 indicates the instruction is specific for DE and RC_12 indicates the instruction is specific for HL. The output of the flip flop swaps the signals that go to the register file (/reg_de_rw and /reg_hl_rw (typo in schematic)).

Schematic of the 8085 circuit to select the DE or HL registers. The flip flop in at the bottom switches the role of DE and HL in response to an XCHG instruction.

Notes and references

The best discussion I've found of the 8085's internal registers and a cycle-by-cycle description of each instruction is "The 8080/8085 microprocessor book", Intel Marketing Communications, Wiley, 1980. (I know a book published by the marketing department sounds lame, but it's actually has some very informative data.) In particular this book describes the data movement in each T-cycle of each instruction, including the WZ, ACT, and TMP registers. Unfortunately this book is long out of print and hard to find.